EP80579 Datasheet, PDF (126/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 3-11. PCI Configuration Header Support for Type 0 Headers in AIOC Devices (Sheet
2 of 2)
Offset Register and Field Bit(s) Supt.^a Acc.^b
Notes
0Ch
0Dh
0Eh
0Fh
Cache Line Size
Latency Timer
Header Type
BIST
7:0
N
7:0
N
7:0
Y
7:0
N
10h - 27h Base Address (x6)
6x
31:0
Y
28h - 2Bh
CIS Pointer
31:0
N
2Ch - 2Dh
Subsystem VID
15:0
Y
2Eh - 2Fh
Subsystem ID
15:0
Y
34h
Capability Pointer
7:0
Y
Y
3Ch
Interrupt Line
7:0
N
3Dh
Interrupt Pin
Y
7:0
N
3Eh
Min_Gnt
7:0
N
3Fh
Max_Lat
7:0
N
RO Not supported.
RO Not supported.
RO Required by PCI.
RO Not supported.
Devices that materialize in I/O or memory
RW spaces will populate these slots as necessary
based on address space needs.
RO Not supported.
RO Required by PCI.
RO Required by PCI.
RO Setup based on capabilities exposure by device.
RW Supported in devices that can use INTx^c.
RO Not supported in devices that do not use INTx^d.
RO Supported in devices that can use INTx^c.
RO Not supported in devices that do not use INTx^d.
RO Not supported.
RO Not supported.
a. Supported fields provide appropriate PCI semantics. Unsupported fields always return zero on reads unless
otherwise noted.
b. RO and RW access types indicate that the register or field supports read-only access and read/write access,
respectively.
c. AIOC devices that may signal via INTx include GbE, CAN, SSP, and IEEE1588.
d. AIOC devices that cannot signal via INTx include LEB.
e. This behavior is a deviation from the PCI specification for only the GbE and a device that can be a bus master.
Table 3-12 summarizes the fields in a PCI type 1 header (i.e., header for bridge
devices) and identifies which fields the EP80579 implements. The EP80579 hardware
implements the appropriate PCI semantics for all supported registers and fields in this
table.
Intel^® EP80579 Integrated Processor Product Line Datasheet
126
August 2009
Order Number: 320066-003US