EP80579 Datasheet, PDF (1279/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.9.1.8 Offset 0Eh: HDR – Header Type Register
Table 35-68. Offset 0Eh: HDR: Header Type Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: 0Eh
Offset End: 0Eh
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: 0Eh
Offset End: 0Eh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
HDR
PCI Header Type: The header type of the device.
00h = single-function device with standard header layout.
Bit Reset
Value
0h
Bit Access
RO
35.9.1.9
Offset 10h: CSRBAR – Control and Status Registers Base
Address Register
The CSRBAR is a PCI BAR in memory space that allows access to the CAN controllers in
the AIOC. See Section 39.6, “Register Summary” on page 1585 for a description of the
individual registers that this region exposes.
Table 35-69. Offset 10h: CSRBAR: Control and Status Registers Base Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: 10h
Offset End: 13h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 12
11 : 04
03
02 : 01
00
Bit Acronym
Bit Description
Sticky
ADDR
ZERO
PREF
TYP
MEM
Upper Programmable Base Address: These bits are set
by BIOS to locate the base address of the region.
Lower Bits: Hardwired to 0 to set the region size to 4KB.
Prefetchable: Hardwired to 0 to indicate that the region is
not prefetchable.
Addressing Type: Hardwired to 0 to indicate a 32-bit
region.
Memory Space Indicator: Hardwired to 0 to identify the
region as in memory space.
Bit Reset
Value
0h
0h
0h
00b
0h
Bit Access
RW
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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