EP80579 Datasheet, PDF (1190/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.5.3.10 Offset 07h: SCR - Scratchpad Register
This 8-bit read/write register has no effect on the UART. It is intended as a scratchpad
register for use by the programmer.
Table 33-22. Offset 07h: SCR - Scratchpad Register
Description:
View: IA F
Base Address: Base (IO)
Size: 8 bit
Default: 00h
Bit Range
07 :00
Bit Acronym
Bit Description
SP_7_0 No effect on UART functionality
Offset Start: 07h
Offset End: 07h
Power Well: Core
Sticky
Bit Reset
Value
00h
Bit Access
RW
33.5.3.11 Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch
Register Low
See Section 33.5.2.1, “Programmable Baud Rate Generator” on page 1174.
Table 33-23. Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register
Low
Description:
View: IA F
Base Address: Base (IO) (DLAB = 1)
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 02h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
BR_7_0 Low byte compare value to generate baud rate
Sticky
Bit Reset
Value
02h
Bit Access
RW
33.5.3.12 Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch
Register High
See Section 33.5.2.1, “Programmable Baud Rate Generator” on page 1174.
Table 33-24. Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register
High
Description:
View: IA F
Base Address: Base (IO) (DLAB = 1)
Offset Start: 01h
Offset End: 01h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
BR_15_8 High byte compare value to generate baud rate
Sticky
Bit Reset
Value
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1190
August 2009
Order Number: 320066-003US