EP80579 Datasheet, PDF (1121/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.3 MICW3 - Master Initialization Command Word 3 Register
Table 30-8. MICW3 - Master Initialization Command Word 3 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 21h
Offset End: 21h
Size: 8 bit
Default: 04h
Power Well: Core
Bit Range
07 : 03
02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
CCC
Reserved
Reserved. Must be programmed to zero.
Cascaded Controller Connection: This bit must always
be programmed to a 1.
This bit indicates that the slave controller is cascaded on
IRQ2. When IRQ8#–IRQ15 is asserted, it goes through
the slave controller’s priority resolver. The slave
controller’s INTR output onto IRQ2. IRQ2 then goes
through the master controller’s priority solver. If it wins,
the INTR signal is asserted to the processor, and the
returning interrupt acknowledge returns the interrupt
vector for the slave controller.
Reserved. Must be programmed to zero.
Bit Reset
Value
0h
1
0h
Bit Access
WO
30.2.2.4 SICW3 - Slave Initialization Command Word 3 Register
Table 30-9. SICW3 - Slave Initialization Command Word 3 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: A1h
Offset End: A1h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 03
02 : 00
Bit Acronym
Bit Description
Sticky
Reserved
SIC
Reserved. Must be programmed to zero.
Slave Identification Code: These bits are compared
against the slave identification code broadcast by the
master controller from the trailing edge of the first
internal INTA# pulse to the trailing edge of the second
internal INTA# pulse. These bits must be programmed to
02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the
INTA# sequence, the slave controller assumes
responsibility for broadcasting the interrupt vector.
Bit Reset
Value
0h
0h
Bit Access
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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