EP80579 Datasheet, PDF (1514/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.18 FCRUC – FC Received Unsupported Count Register
This register counts the number of unsupported flow control frames that are received.
This counter is incremented when a packet is received which matches either the
reserved flow control multicast address (in FCAH/FCAL) or the MAC station address,
has a matching flow control type field match (to the value in FCT), but has an incorrect
opcode field. This register will only increment if the driver has receives enabled.
Table 37-96. FCRUC: FC Received Unsupported Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4058h
Offset End: 405Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4058h
Offset End: 405Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4058h
Offset End: 405Bh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
FCRUC
Number of unsupported flow control frames received
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.19 PRC64 – Good Packets Received Count (64 Bytes) Register
This register counts the number of good packets (no link or CRC error) received that
are exactly 64B (from <Destination Address> through <CRC>, inclusively) in length.
Hardware flow-control packets are not included in this count. This register includes
good regular packets received to the Receive Packet Buffer. Packets identified as Missed
Packets due to Receive Packet Buffer overruns are not included in this count (refer to
the “MPC – Missed Packet Count Register” on page 1507).
Table 37-97. PRC64: Good Packets Received Count (64 Bytes) Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 405Ch
Offset End: 405Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 405Ch
Offset End: 405Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 405Ch
Offset End: 405Fh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
PRC64
Number of good packets received exactly 64 bytes in
length.
Sticky
Bit Reset
Value
Bit Access
0h
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1514
August 2009
Order Number: 320066-003US