EP80579 Datasheet, PDF (278/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.2
Note:
IMCH Responses to EDMA Transactions
In the following tables, the term “Abort” implies that the EDMA engine will immediately
stop the transfer in progress. The offending access will not be forwarded to the
inbound/outbound arbiter at all, an error bit will be set accordingly, and the error will
be escalated as specified by the configuration bits controlling interrupts and errors.
This behavior is quite different from the and PCI Express inbound ports, as in the latter
cases the transaction in question was requested by some other initiator elsewhere in
the platform. The EDMA engine is a source of traffic all by itself, which makes error
containment much simpler in the case of EDMA traffic.
10.2.1
Fixed Address Spaces (EDMA)
Table 10-14 summarizes IMCH responses to EDMA accesses to the various fixed
address spaces.
Table 10-14. EDMA Accesses to Fixed Address Spaces
Address
Space
DOSMEM
VGAA
VGAB
MDA
PAMC0…
PAMF0
MEM1_15
ISA15
MAINMEM
TSEGSMM
IOAPIC[0,2-3]
FSBINTR
HIGHSMM
HIGHMEM
Conditions
-
-
-
FDHC.HEN = 0
FDHC.HEN = 1
-
-
-
-
-
Address is below the top of
memory space defined by
TOM and the REMAP
registers
Address is above the top of
memory
Destination
MainMem
Abort
MainMem
MainMem
Abort
MainMem
Variable
Abort
Abort
Variable
MainMem
Abort
IMCH Response
Transaction is sent to memory system
Programmer’s responsibility not to target
EDMA accesses in the legacy region
between 640KB and 1 MByte
Transaction is sent to memory system
Hole Disabled: Transaction is sent to
memory system
Hole Enabled: EDMA will abort on accesses
directed to the ISA hole when enabled
Transaction is sent to memory system
(unless address hits an enabled TSEG SMM
range. See TSEGSMM)
Refer to Table 10-16, “Supported SMM
Ranges”.
Programmer’s responsibility to avoid the
APIC ranges
Programmer’s responsibility to avoid the
FSB interrupt messaging range
Refer to Table 10-16, “Supported SMM
Ranges”.
Transaction is sent to memory system.
Hardware will detect an attempt to access
above the populated DRAM space, and will
abort.
10.2.2
Relocatable Address Spaces (EDMA)
Table 10-15 summarizes IMCH responses to EDMA accesses to the various relocatable
address spaces.
Intel^® EP80579 Integrated Processor Product Line Datasheet
278
August 2009
Order Number: 320066-003US