EP80579 Datasheet, PDF (264/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
9.6
9.6.1
9.6.2
Note:
9.6.3
9.6.4
9.6.5
IICH Feature List
This section provides a listing of architectural functionality for the major features of the
IICH. Detailed usage information and operational flows, internal register bit
information, and other specific details of the implementation are provided later in this
document.
Low-Pin count (LPC) Interface and Firmware Hub (FWH)
Interface
• Allows connection of devices such as Super I/O, micro controllers, customer ASICs.
• Supports two master/DMA devices.
• Memory size up to 8 Mbit.
Serial Peripheral Interface (SPI)
Intel recommends using the SPI as your boot interface.
• Supports multiple SPI Flash vendors.
• Simplified Hardware.
• Equivalent to LPC-based Firmware Hubs.
Integrated Serial ATA Host Controllers
• Independent DMA operation on two ports.
— Two ports in SATA 1.0a and AHCI mode.
— Two ports in AHCI mode only.
• Data transfer rates up to 300 Mbyte/s.
• Support Gen2m electrical spec (cable not exceeding 2m).
USB
• One EHCI USB 2.0 Host Controller with a total of two ports (shared with the UHCI
ports).
• One UHCI Host Controller for a total of two ports (shared with the EHCI ports).
• Supports a Debug Port at USB 2.0 transfer rates.
Interrupt Controller
• Supports up to 8 PCI interrupt pins.
• Two cascaded 82C59 with 15 interrupts.
• Integrated I/O APIC supports a total of 40 interrupts (24 interrupts only, when
ETR3.GPIO_IRQ_STRAP_STS is 0).
• Serial Interrupt input for ISA legacy-compatible and PCI interrupts.
• Supports PCI scheme for delivering interrupts as write cycles (rather than via
PIRQ[A-H]#).
• Front-Side Message Interrupt Delivery.
• Supports EOI message.
Intel^® EP80579 Integrated Processor Product Line Datasheet
264
August 2009
Order Number: 320066-003US