EP80579 Datasheet, PDF (1883/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 49-34.GbE RGMII Mode Signal Connection Block Diagram
RGMII signals
GbEn MAC
GBEn_TxCLK
GBEn_TXCTL
GBEn_TxDATA[3:0]
125/25/2.5 MHz
1000/100/10 Base PHY
GTX_CLK
TX_EN
TXD[3:0]
GBEn_RxCLK
GBEn_RXCTL
GBEn_RxDATA[3:0]
GBE
I/O Vcc
GBE_REFCLK
125/25/2.5 MHz
125 MHz
Source Clock
RX_CLK
RX_DV
RXD[3:0]
125 MHz Ref Clk
GBE
I/O Vcc
Vcc
2.5V ± 5%
B6573-01
49.5.13.3.3 GbE Ethernet Interface — RGMII Mode Reference Clock
Table 49-76 shows the RGMII 125 MHz reference clock AC specifications.
Table 49-76. GbE RGMII Reference Clock Timing Values
Symbol
Parameter
Min
Nominal
Max
Units Notes
T₁
RGMII reference clock period
Frequency accuracy
-
8.0
-
ns
1
-50
-
+50
ppm
1
T₂
T₃
T₄
T_jitter
Duty cycle with respect to T₁ (Nom.)
Low to high rise time (20% to 80%)
High to low fall time (80% to 20%)
Cycle to Cycle Jitter
Peak to peak Jitter (aggregate)
45
50
55
%
1, 5
-
-
0.75
ns
2, 5
-
-
0.75
ns
3, 5
-
-
80
ps
4, 5
-
-
150
ps
4, 5
Notes:
1.
Applies to GBEn_REFCLK signal operating in RGMII mode.
2.
Measurement points for Rise time are 20% GBE V_CC to 80% GBE V_CC.
3.
Measurement points for Fall time are 80% GBE V_CC to 20% GBE V_CC.
4.
The maximum allowable jitter is 80 ps. This jitter can be less but never greater than 80 ps. This
reference clock jitter directly translates into the jitter produced on the GBEn_TxCLK signal. For
example, a 40 ps jitter on the reference clock input would generate the same 40 ps jitter on the
GBEn_TxCLK signal.
5.
Guaranteed by design. These values are typical values seen for this process, but not measured
during production testing.
Figure 49-35 shows the RGMII 125 MHz reference clock timing diagram.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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