EP80579 Datasheet, PDF (787/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 21-1. Basic SPI Protocol
C LK
C S!
MOS I
M IS O
Bit 3
Bit2
Bit1
B it 0
Bit3
Bit 2
Bit 1
Bit0
C LK
C S!
MOS I
M IS O
Bit 3
Bit2
Bit1
B it 0
Bit3
Bit 2
Bit 1
Bit0
21.3.1.1
21.3.1.2
Only Mode 0 is supported.
Commands, Addresses and Data are shifted most significant bit (MSB) first. For the 24-
bit address, this means bit 23 is shifted first while bit 0 is shifted last. However, for data
bursts, bytes are shifted out from least significant byte to most significant byte, where
each byte is shifted (MSB to LSB).
Addressing
A Slave is targeted for a cycle when it’s SPI_CS# pin is asserted. Besides Slave
addressing there is register addressing within the Slave itself. The list of EP80579
supported devices’ includes only FLASH devices. See supported devices data sheets for
more information.
Data Transaction
All transactions on the SPI bus must be a multiple of 8 bits. A frame consists of any
number of 8-bit data packets. To initiate a data transfer, the SPI Master asserts (high to
low transition) the SPI_CS# signal informing the SPI Slave that it is being targeted for
a cycle. The Master will then shift out the 8-bit opcode followed by the Slave’s internal
address.
In the case of a Read transaction, the Slave will interpret the Slave address and begin
driving data out on the SPI_MISO pin and ignore any transactions on the SPI_MOSI
pin. The Master indicates Read complete by deasserting the SPI_CS# signal on an 8-bit
boundary.
In the case of a Write transaction, the Slave will continue to receive Master data on the
SPI_MOSI pin. The Write transaction is completed upon deassertion of the SPI_CS#
signal on an 8-bit boundary.
The SPI bus does include a mechanism for flow control, however some devices include
the support of a HOLD signal. See Slave documentation for more information. If the
Slave receives an un-recognized or invalid opcode it should ignore the rest of the
packet and wait for the deassertion of SPI_CS#.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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