EP80579 Datasheet, PDF (1332/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.12.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID Register
The Message Signalled Interrupt Capability record defines how the device generates
PCI MSI messages. It is an 10B PCI SIG-defined capability record and includes the
MCID, MCP, MCTL, MADR, and MDATA fields of the configuration header.
Table 35-176.Offset F0h: MCID: Message Signalled Interrupt Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: F0h
Offset End: F0h
Size: 8 bit
Default: 05h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
MCID
Capability ID: PCI SIG assigned capability record ID
(05h, MSI capability)
Sticky
Bit Reset
Value
Bit Access
05h
RO
35.12.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register
Table 35-177.Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer
Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: F1h
Offset End: F1h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
MCP
Next Capability Pointer: Hardwired to 0 to indicate this
is the last capability.
Bit Reset
Value
0h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1332
August 2009
Order Number: 320066-003US