EP80579 Datasheet, PDF (310/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 12-2. Conceptual Diagram of Four Channel EDMA Engine
FSB Interface
Cfg/TAP Interface
EDMA Channel0
EDMA Channel1
EDMA Channel2
EDMA Channel3
EDMA Arbiter
REQs
GNTs
System Arbiter
12.2
Channel Programming Interface
The EDMA channel programming interface is accessible from the IA-32 core via a
combination of chain descriptors (shown in Figure 12-3) written to main memory and a
memory-mapped internal register set. The EDMA controller provides four channels,
each of which can be independently used to transfer data within the local system
memory or from the local system memory to the I/O subsystem. Each channel has its
own set of 12 registers. Refer to “Memory Mapped I/O for EDMA Registers” on
page 651 for a description of the channel register set.
The channel programming interface is accessible from the IA-32 core via a combination
of descriptors written to main memory and a memory-mapped internal register set.
Each channel is programmed independently.
Each channel supports full chaining capability. The chain descriptors can be cascaded
together in system memory to form a linked list. Each chain descriptor contains all the
information necessary for transferring a block of data, as well as a pointer to the next
chain descriptor in the list. The next descriptor pointer of the last chain descriptor in a
linked list will be a null pointer (address zero), indicating the end of that chain.
Intel^® EP80579 Integrated Processor Product Line Datasheet
310
August 2009
Order Number: 320066-003US