EP80579 Datasheet, PDF (60/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16-24
16-25
16-26
16-27
16-28
16-29
16-30
16-31
16-32
16-33
16-34
16-35
16-36
16-37
16-38
16-39
16-40
16-41
16-42
16-43
16-44
16-45
16-46
16-47
16-48
16-49
16-50
16-51
16-52
16-53
16-54
16-55
16-56
16-57
16-58
16-59
16-60
16-61
16-62
16-63
16-64
16-65
16-66
16-67
16-68
16-69
16-70
16-71
16-72
16-73
16-74
Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register ................................. 406
Offset 5FH: PAM6 - Programmable Attribute Map 6 Register ................................. 407
Offset 9Ch: DEVPRES - Device Present Register .................................................. 408
Offset 9Dh: EXSMRC - Extended System Management RAM Control Register ........... 409
Offset 9Eh: SMRAM - System Management RAM Control Register .......................... 411
Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register ...... 413
Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Base
Address Register ............................................................................................ 413
Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct) Memory
Limit Address Register ..................................................................................... 414
Offset C4h: TOLM - Top of Low Memory Register ................................................. 415
Offset C6h: REMAPBASE - Remap Base Address Register ..................................... 416
Offset C8h: REMAPLIMIT – Remap Limit Address Register ..................................... 416
Offset CAh: REMAPOFFSET - Remap Offset Register ............................................ 417
Offset CCh: TOM - Top Of Memory Register ........................................................ 417
Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base Address
Register ......................................................................................................... 418
Offset D8h: CACHECTL0 - Write Cache Control 0 Register .................................... 418
Offset DEh: SKPD - Scratchpad Data Register ..................................................... 419
Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register ........................................... 419
DRB to DIMM designation .................................................................................. 420
Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register ................................. 421
DRA[1:0] Field Selection.................................................................................... 422
Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register .................................. 422
Offset 78h: DRT0 - DRAM Timing Register 0 ........................................................ 424
Offset 64h: DRT1 - DRAM timing Register 1 ........................................................ 431
Offset 7Ch: DRC - DRAM Controller Mode Register .............................................. 435
Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register ..................... 437
Offset 88h: SDRC - DDR SDRAM Secondary Control Register ................................ 439
Offset 8Ch: CKDIS - CK/CK# Clock Disable Register ............................................ 441
Offset 8Dh: CKEDIS - CKE Clock Enable Register ................................................ 442
Offset 90h: SPARECTL - SPARE Control Register .................................................. 443
Offset B0h: DDR2ODTC - DDR2 ODT Control Register ........................................... 444
Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration
Registers ......................................................................................................... 445
Offset 00h: VID - Vendor Identification Register .................................................. 447
Offset 02h: DID - Device Identification Register ................................................... 447
Offset 04h: PCICMD - PCI Command Register ..................................................... 448
Offset 06h: PCISTS - PCI Status Register ........................................................... 448
Offset 08h: RID - Revision Identification Register ................................................ 449
Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 449
Offset 0Bh: BCC - Base Class Code Register ....................................................... 449
Offset 0Dh: MLT - Master Latency Timer Register ................................................ 450
Offset 0Eh: HDR - Header Type Register ............................................................ 450
Offset 2Ch: SVID - Subsystem Vendor Identification Register ............................... 450
Offset 2Eh: SID - Subsystem Identification Register ............................................ 451
Offset 40h: GLOBAL_FERR - Global First Error Register ........................................ 451
Offset 44h: GLOBAL_NERR - Global Next Error Register ....................................... 453
Offset 48h: NSI_FERR - NSI First Error Register .................................................. 454
Offset 4Ch: NSI_NERR - NSI Next Error Register ................................................. 457
Offset 50h: NSI_SCICMD - NSI SCI Command Register ....................................... 459
Offset 54h: NSI_SMICMD: NSI SMI Command Register ........................................ 461
Offset 58h: NSI_SERRCMD - NSI SERR Command Register .................................. 464
Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register .............................. 466
Offset 60h: FSB_FERR - FSB First Error Register ................................................. 468
Intel^® EP80579 Integrated Processor Product Line Datasheet
60
August 2009
Order Number: 320066-003US