EP80579 Datasheet, PDF (224/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.4
7.4.1
AIOC Registers
This section summarizes the registers in the AIOC. The registers are presented as they
materialize from a PCI perspective.
PCI-to-PCI Bridge: Bus 0, Device 4, Function 0
The PCI-to-PCI Bridge includes the registers listed in Table 7-46. These registers
materialize in PCI configuration space. See Chapter 34.0, “PCI-to-PCI Bridge Detailed
Register Descriptions” for detailed discussion of these registers along with alternative
materializations.
Table 7-46. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
0h
2h
4h
6h
8h
9h
Ch
Dh
Eh
10h
14h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
20h
22h
24h
26h
28h
2Ch
30h
32h
34h
3Ch
1h
3h
5h
7h
8h
Bh
Ch
Dh
Eh
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Fh
21h
23h
25h
27h
28h
2Ch
31h
33h
34h
3Ch
“Offset 0h: VID: Vendor Identification Register” on page 1217
“Offset 2h: DID: Device Identification Register” on page 1217
“Offset 4h: PCICMD: Device Command Register” on page 1217
“Offset 6h: PCISTS: PCI Device Status Register” on page 1218
“Offset 8h: RID: Revision ID Register” on page 1219
“Offset 9h: CC: Class Code Register” on page 1219
“Offset Ch: CLS: Cacheline Size Register” on page 1219
“Offset Dh: LT: Latency Timer Register” on page 1220
“Offset Eh: HDR: Header Type Register” on page 1220
“Offset 10h: CSRBAR0: Control and Status Registers Base Address Register” on
page 1220
“Offset 14h: CSRBAR1: Control and Status Registers Base Address Register” on
page 1221
“Offset 18h: PBNUM: Primary Bus Number Register” on page 1221
“Offset 19h: SECBNM: Secondary Bus Number Register” on page 1221
“Offset 1Ah: SUBBNM: Subordinate Bus Number Register” on page 1222
“Offset 1Bh: SECLT: Secondary Latency Timer Register” on page 1222
“Offset 1Ch: IOB: I/O Base Register” on page 1222
“Offset 1Dh: IOL: I/O Limit Register” on page 1223
“Offset 1Eh: SECSTA: Secondary Status Register” on page 1223
“Offset 20h: MEMB: Memory Base Register” on page 1224
“Offset 22h: MEML: Memory Limit Register” on page 1224
“Offset 24h: PMASE: Prefetchable Memory Base Register” on page 1225
“Offset 26h: PMLIMIT: Prefetchable Memory Limit Register” on page 1225
“Offset 28h: PMBASU: Memory Limit Register” on page 1226
“Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register” on page 1226
“Offset 30h: IOBU: I/O Base Upper Register” on page 1227
“Offset 32h: IOLU: I/O Limit Upper Register” on page 1227
“Offset 34h: CP: Capabilities Pointer Register” on page 1227
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1228
8086h
5037h
0h
10h
Variable
060400h
00h
00h
1h
00h
00h
00h
00h
00h
00h
F0
0
0h
FFF0
0
FFF1H
1H
Fh
0
0
0
dch
0
Intel^® EP80579 Integrated Processor Product Line Datasheet
224
August 2009
Order Number: 320066-003US