EP80579 Datasheet, PDF (1072/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-20. Offset 34h: SMI_STS - SMI Status Register (Sheet 2 of 3)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 34h
Offset End: 34h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
12
11
10
09
08
07
06
Bit Acronym
Bit Description
Sticky
This read-only bit is set when bit 0 in the DEVTRAP_STS
DEVMON_STS
register is set. It is not sticky, so writes to this bit will
have no effect.
See Section 27.3.1.3.]
MCSMI_STS
0 = Indicates that there has been no access to the
power management microcontroller range (62h or
66h).
1 = Set if there has been an access to the power
management microcontroller range (62h or 66h)
and the Microcontroller Decode Enable #1 bit in the
LPC Bridge I/O Enables configuration register is 1.
Note that this implementation assumes that the
Microcontroller is on LPC, if this changes in the
future (i.e. PCI e-based SIO), then the
implementation will need to remove the LPC
Decode Enable dependency. If this bit is set, and
the MCSMI_EN bit is also set, CMI will generate an
SMI#.
This bit is set by hardware and cleared by software
writing a 1 to its bit position.
GPE1_STS
This bit is a logical OR of the bits in the
ALT_GPI_SMI_STS register that are also set up to cause
an SMI# (as indicated by the GPI_ROUT registers) and
have the corresponding bit set in the ALT_GPI_SMI_EN
register.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
Bits that are not routed to cause an SMI# will have no
effect on this bit. This bit is NOT sticky. Writes to this bit
will have no effect.
GPE0_STS
This bit is a logical OR of bits 13, 11, 8:6, 4:3 and 0 in
the GPE0_STS register (PMBASE + 28h) that also have
the corresponding bit set in the GPE0_EN register
(PMBASE + 2Ch). This bit is NOT sticky.
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
Note: Writes to this bit will have no effect. The setting
of this bit does not cause the SMI#
Note: Bits 31:16 of the GPE0_STS register are not
capable of generating SMIs; therefore, they do
not set this SMI status bit.
This is an OR of the bits (except for bits 5 and 4) in the
ACPI PM1 Status Reg. (offset PMBASE+00h). Not sticky.
Writes to this bit have no effect.
0 = SMI# was not generated by a PM1_STS event.
PM1_STS_REG ^{1 = SMI# was generated by a PM1_STS event.}
This bit gets set when PM1_STS.TMROF_STS gets set.
Hence, it is highly likely that a read to this register after
reset will yield a 1 in this field.
Note: The setting of this bit does not cause the SMI#.
Reserved Reserved.
SWSMI_
TMR_STS
0 = Software SMI# Timer has Not expired.
1 = Set by the hardware when the Software SMI#
Timer expires.
This bit will remain 1 until the software writes a 1 to this
bit.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
Bit Access
RO
RWC
RO
RO
RO
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1072
August 2009
Order Number: 320066-003US