EP80579 Datasheet, PDF (420/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.39 Offset 60h: DRB[0-3] – DRAM Row [3:0] Boundary Register
DRAM row boundary register defines the upper boundary address for each DRAM row
with a granularity of 64MB. Each row has its own single byte DRB register. The value in
a given DRB corresponds to the cumulative memory size including that row. For
example, a value of 1 (0000 0001) in DRB0 (address lines 33 to 26) indicates that 64
Mbytes of DRAM has been populated in the first row.
DRB0 = Total memory in row0 (64 Mbyte increments)
DRB1 = Total memory in row0 + row1 (64 Mbyte increments)
DRB2 = Total memory in row0 + row1 + row2 (64 Mbyte increments)
DRB3 = Total memory in row0 + row1+ row2 + row3 (64 Mbyte increments)
The functionality of DRB3 is somewhat different than DRB[2:0]. In order to avoid a
64MByte “hole” at the top of memory, a value of 0x00 in DRB3, is interpreted as 0x100.
In practice, this 0x00 value should not be set, since it implies addressing more memory
than the EP80579 supported.
Note:
The memory controller does not implement any hardware checks to prevent accesses
to DRAM locations beyond what is populated in the DRB3 register. Such accesses are
software programming errors and will result in unreliable operation.
Table 16-41 shows the DRBx to DIMM mapping. Please note that before populating the
DIMM’s, all limitation described in Section 11.3.1, “Rules for Populating DIMM Slots”
need to be followed.
Table 16-41. DRB to DIMM designation
Even Row
Row/DRB
Number
Address or DRB
DIMM0
DRB0
60h
DIMM1
DRB2
62h
Odd Row
Row/DRB
Number
Address or DRB
DRB2
62h
NA
NA
Rules for programming the DRBx registers:
• DRB1 and DRB3 are unused and reserved.
— DRB1 and DRB3 should be programmed to be the same value as what was
programmed in the even row. (DRB1 = DRB0, DRB3 = DRB2).
• Unpopulated rows must be programmed with a value of the last populated slot.
This guarantees the unpopulated row will not be selected.
• Depending upon the configuration and amount of memory populated in each row,
DRB0 and DRB2 should be programmed. This will correspond to on the EP80579,
CS0# and CS1#.
— Single rank, 1 DIMM system programs DRB0 with the encoding for memory
capacity in row 0. Further, DRB1 = DRB2 = DRB3 = DRB0.
— Single ranks in a 2 DIMM system programs DRB0 with the encoding for
memory capacity in row 0 and DRB2 with the encoding for memory capacity in
row 0 + row 1 + row 2. Further, DRB1 = DRB0 and DRB3 = DRB2.
Intel^® EP80579 Integrated Processor Product Line Datasheet
420
August 2009
Order Number: 320066-003US