EP80579 Datasheet, PDF (1006/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The second set at offsets 60h to the end of the implemented register space are
implemented in the Suspend power well. Unless otherwise noted, the core-well
registers are reset by the assertion of either of the following:
• suspend well hardware reset
• HCRESET
The default values are defined with an h for hex, a b for binary, or 00 for zero. If there
is not a letter following the default value, assume it is a binary number.
Warning:
Address locations that are not listed are considered reserved registers locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Note:
Reserved bits are Read Only.
Table 26-39. Host Controller Operational Register Details Summary Table
MEM_BASE +
Offset
Start
End
Symbol
Register Name/Function
Default
Special
Notes
20
23h
USB
2.0CMD
USB 2.0 Command Register
00080000h
24
27h USB 2.0STS USB 2.0 Status Register
00001000h
28
2Bh
USB
2.0INTR
USB 2.0 Interrupt Enable Register
00000000h
2C
2Fh
FRINDEX USB 2.0 Frame Index Register
00000000h
30
33h
CTRLDSSEG Control Data Structure Segment
MENT
Register
00000000h
34
37h
PERIODICLI Period Frame List Base Address
STBASE Register
00000000h
38
3Bh
ASYNCLIST Next Asynchronous List Address
ADDR
Register
00000000h
60
63h
CONFIG
FLAG
Configure Flag Register
00000000h
Suspend
64
67h
PORTSC Port 1 Status and Control Register 00003000h
Suspend
68
6Bh
PORTSC Port 2 Status and Control Register 00003000h
Suspend
A0
B3h
Debug Port Registers (see Section 26.13.2,
“Debug Port Register Details”)
Access
RW
RWC, RO
RW
RW, RO
RW
RW
RW, RO
RW, RO
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1006
August 2009
Order Number: 320066-003US