EP80579 Datasheet, PDF (376/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 15-10. Offset 04-07: DATA - Data Register
Bits
31:24
23:16
15:08
07:00
Type
RW
RW
RW
RW
Reset
00h
00h
00h
00h
Description
Byte 3 (DATA3): Data bits [31:24]
Byte 2 (DATA2): Data bits [23:16]
Byte 1 (DATA1): Data bits [15:8]
Byte 0 (DATA0): Data bits [7:0]
15.2.1.3.8
STS – Status Register
For a read cycle, the data is preceded by a byte of status. Table 15-11 shows how these
bits are defined.
Table 15-11. Status Register
Position
Description
07
06
05
04
03:01
00
Internal Timeout
0 = SMBus request is completed within 2 ms internally
1 = SMBus request is not completed in 2 ms internally
Ignored
Internal Master Abort
0 = No Internal Master Abort Detected
1 = Detected an Internal Master Abort
Internal Target Abort
0 = No Internal Target Abort Detected
1 = Detected an Internal Target Abort
Ignored
Successful
0 = The last SMBus transaction was not completed successfully
1 = The last SMBus transaction was completed successfully
15.2.1.4
15.2.1.5
Unsupported Access Addresses
It is possible for an SMBus master to program an unsupported bit combination into the
ADDR registers. The IMCH does not support such usage, and may not gracefully
terminate such accesses.
SMBus Transaction Pictograms
Since the new SMBus target interface is of enterprise origin, it is more complex than
the original SMBus target interface of desktop origin. The following drawings are
included to demonstrate the different types of transactions, especially how they can be
broken up into multiple smaller transfers.
Intel^® EP80579 Integrated Processor Product Line Datasheet
376
August 2009
Order Number: 320066-003US