EP80579 Datasheet, PDF (84/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
41-29
41-30
41-31
41-32
41-33
41-34
41-35
41-36
41-37
41-38
41-39
41-40
41-41
41-42
41-43
42-1
42-2
42-3
42-4
42-5
42-6
42-7
42-8
42-9
42-10
42-11
43-1
43-2
43-3
43-4
44-1
44-2
45-1
45-2
45-3
46-1
46-2
46-3
47-1
47-2
47-3
47-4
48-1
48-2
48-3
Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register
(Per Ethernet Channel) .................................................................................... 1659
Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register
(Per Ethernet Channel) .................................................................................... 1660
Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register
(Per Ethernet Channel) .................................................................................... 1661
Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register
(Per Ethernet Channel) .................................................................................... 1662
Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register
(Per Ethernet Channel) .................................................................................... 1663
Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register
(Per Ethernet Channel) ................................................................................... 1664
Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel) ............................................................................. 1665
Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register
(Per CAN Channel).......................................................................................... 1666
Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register
(Per CAN Channel).......................................................................................... 1667
Offset 01F0h: TS_Aux_TrgtLo Register ............................................................. 1668
Offset 01F4h: TS_Aux_TrgtHi Register .............................................................. 1668
Offset 0200h: L2 EtherType Register ................................................................. 1669
Offset 0204h: User Defined EtherType Register .................................................. 1669
Offset 0208h:User Defined Header Offset Register .............................................. 1670
Offset 020Ch:User Defined Header Register ....................................................... 1670
Example Expansion Bus Pin Mappings to Target Devices ...................................... 1673
Expansion Bus Address and Data Byte Steering ................................................. 1676
Multiplexed Output Pins for HPI Operation.......................................................... 1682
HPI HCNTL Control Signal Decoding .................................................................. 1682
Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through
CSRBAR PCI Memory BAR"............................................................................... 1697
EXP_TIMING_CS0 - Expansion Bus Timing Register ............................................. 1698
EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers .................................... 1700
EXP_CNFG0 -Configuration Register 0 ............................................................... 1702
EXP_PARITY_STATUS - Expansion Bus Parity Status Register .............................. 1703
LEB Performance Calculation - Estimated AIOC Latencies ..................................... 1704
Outbound Performance Estimation Examples ...................................................... 1705
EP80579 TAPs Public Instructions...................................................................... 1710
EP80579 TAP IDCode Values ............................................................................ 1710
JTAG Instructions Summary for MCH ............................................................... 1711
Compliance Pins Excluded from Boundary Scan Chain .......................................... 1713
1149.1 Public Instructions in the IA-32 Core TAP ............................................... 1715
Device ID Register Bit-fields ............................................................................ 1716
IMCH JTAG Instructions .................................................................................. 1717
JTAG Device Identification Register Field Designations ........................................ 1718
JTAG ID Code for CMI ..................................................................................... 1718
Serial Test Mode Entry Command Field .............................................................. 1722
Test Control Register 0 ................................................................................... 1723
XOR Chains.................................................................................................... 1725
Base Features of EP80579 SKUs ....................................................................... 1730
IA-32 Core Internal Bus and DDR2 Frequencies .................................................. 1731
Tolapai Strap Options ...................................................................................... 1731
EP80579 Pre-Boot Firmware Programmable Options ............................................ 1732
Signal Type Definitions .................................................................................... 1733
XOR Chain Elements ....................................................................................... 1734
Signal Pin Description References ..................................................................... 1735
Intel^® EP80579 Integrated Processor Product Line Datasheet
84
August 2009
Order Number: 320066-003US