EP80579 Datasheet, PDF (90/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Revision History
Date
Revision Description
Added:
• Chapter 28.0, “IA-32 Core Interface”
December
2008
July 2008
Updated:
• Figure 6-1, “Powergood and Reset Interface”
• Table 49-12, “Power Sequencing Signal Timings”
• Table 16-26, “Offset 9Ch: DEVPRES - Device Present Register”
• Table 16-40, “Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register”
• Section 22.1, “Overview”
• Text in Section 35.12.1.9, “Offset 14h: MMBAR – Expansion Bus Base Address Register”
• Text in Section 42.5.1.2, “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers”
• Figure 42-2, “Chip Select Address Allocation When There Are no 32-MByte Devices Programmed”
• Figure 42-4, “Chip Select Address Allocation when a 32 Mbyte device is programmed”
• Figure 48-3, “FCBGA Package — Bottom View”
• Table 48-24, “Expansion Bus Signals”
002
• Table 48-29, “Reserved Pin List”
• Table 48-30, “No Connect Pin List”
• Table 49-7, “Maximum Supply Current Embedded SKU”
• Table 49-11, “Power Management DC Output Characteristics”
• Table 49-36, “SMBus DC Input Characteristics”
• Table 49-38, “SMBus DC Clock Specification”
• Table 49-48, “SPI DC Output Characteristics”
• Table 49-67, “DC Output Characteristics: RMII Mode of Operation”
• Table 49-82, “EEPROM Timing Values”
• Table 49-84, “TDM DC Output Characteristics”
• Table 49-89, “LEB DC Output Characteristics”
• Table 49-93, “CAN DC Output Characteristics”
• Table 49-95, “SSP DC Output Characteristics”
• Table 49-99, “IEEE 1588-2008 Hardware Assist DC Output Characteristics”
• Table 49-101, “IICH Miscellaneous Signals DC Output Characteristics”
• Table 49-108, “JTAG DC Output Specifications (BPM4_PRDY_OUT)”
001 Initial release of this document.
Intel^® EP80579 Integrated Processor Product Line Datasheet
90
August 2009
Order Number: 320066-003US