EP80579 Datasheet, PDF (184/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The materialization information in a table includes specification of one or more “views”.
Each view consists of a view “type” along with several type-specific fields that serve to
specify the “address” of the register in the system from a particular perspective. For
example, a PCI “view” includes, in part, the PCI bus number as a parameter since this
information is necessary to specify the location of the register. In a register description
table, each view specification occupies one row of the table. A register description table
includes one or more views depending on how the register materializes to software.
There are a number of different views that this document uses to describe how
EP80579 registers materialize to software. Table 7-1 defines the views that this
document uses along with the type-specific fields that each view includes.
Table 7-1.
Definition of the Views Used in Register Description Tables
View Type
Describes
Registers in
PCI configuration
space or memory/
PCI
IO spaces that are
mapped via PCI
BARs
IA F
General “fixed”
location in IA
memory or I/O
spaces
Name
B:D:F
BAR
Offset Start
Offset End
Base Address
Offset Start
Offset End
Type-Specific Fields
Description
PCI Bus, Device, and Function number that the
register is associated with through PCI configuration,
memory-mapped, or I/O-mapped spaces (see BAR).
PCI base address register in B:D:F that the register is
referenced from. This field is “Configuration” for
registers that materialize in PCI configuration space.
Otherwise, the field is the name of the BAR register in
B:D:F that provides the base address.
The register materializes in memory space unless the
BAR field contains “(IO)”; i.e., views with a BAR of
“FOOBAR” and “FOOBAR (IO)” materialize in memory
and I/O spaces, respectively.
Starting offset from BAR. The offset is in bytes unless
the field contains “(2B)”, “(4B)”, and “(8B)” to indicate
a single-, double-, or quad-word offset, respectively^a.
Ending offset of register from BAR. The offset is in
bytes unless the field contains “(2B)”, “(4B)”, and
“(8B)” to indicate a single-, double-, or quad-word
offset, respectively^a.
Base address. Typically, this field contains a number or
register name. It may contain a comma-separated list
if the register can materialize at one of several
possible bases (for example, “100h, 200h based on
FOOREG”).
The register materializes in memory space unless the
base address field contains “(IO)”; i.e., views with a
base address of “0000h” and “0000h (IO)” are in
memory and I/O space, respectively.
Starting address or offset from base address field. The
offset is in bytes unless the field contains “(2B)”,
“(4B)”, and “(8B)” to indicate a single-, double-, or
quad-word offset, respectively^a.
Ending address or offset from base address field. The
offset is in bytes unless the field contains “(2B)”,
“(4B)”, and “(8B)” to indicate a single-, double-, or
quad-word offset, respectively^a.
Intel^® EP80579 Integrated Processor Product Line Datasheet
184
August 2009
Order Number: 320066-003US