EP80579 Datasheet, PDF (1051/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.1.3 Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register
Table 27-5. Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register (Sheet 1 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: A4h
Offset End: A4h
Size: 8 bit
Default: 00h
Power Well: RTC
Bit Range
07 : 06
05 : 04
03
02
Bit Acronym
Bit Description
Sticky
SWSMI_
RATE_SEL
SMAW
SASE
RPS
This 2-bit value indicates when the SWSMI timer will time
out. Valid values are:
• 00 1.5 ms +/- 0.6 ms
• 01 16 ms +/- 4 ms
• 10 32 ms +/- 4 ms
• 11 64 ms +/- 4 ms
These bits are not cleared by any type of reset except
RTEST#.
SLP_S4# Minimum Assertion Width: This 2-bit value
indicates the minimum assertion width of the SLP_S4#
signal to guarantee that the DRAMs have been safely
power-cycled. This value may be modified per platform
depending on DRAM types, power supply capacitance, etc.
Valid values are:
• 11 1 to 2 seconds
• 10 2 to 3 seconds
• 01 3 to 4 seconds
• 00 4 to 5 seconds
This value is used in two ways:
1. If the SLP_S4# assertion width is ever shorter than this
time, a status bit (D31.F0.A2h.2) is set for BIOS to read
when S0 is entered
2. If enabled by bit 3 in this register, the hardware will
prevent the SLP_S4# signal from deasserting within this
minimum time period after asserting
Note: The logic that measures this time is in the suspend
power well. Therefore, when leaving the G3 state,
the minimum time is measured from the
deassertion of RSMRST#.
RTEST# forces this field to the conservative default state
(00b).
SLP_S4# Assertion Stretch Enable:
0 = The SLP_S4# minimum assertion time is 1 to 2
RTCCLK.
1 = The SLP_S4# signal will minimally assert for the time
specified in bits 5:4 of this register.
This bit is cleared by RTEST#.
RTC Power Status:
0 = RTEST# OK
1 = RTEST# indicates a weak or missing battery. The bit
remains set until the software clears it by writing a 0
back to this bit position.
This bit is not cleared by any type of reset.
Bit Reset
Value
00h
00h
0h
X
Bit Access
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1051