EP80579 Datasheet, PDF (1266/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.8.1.2
Offset 02h: DID – Device Identification Register
This 16-bit register combined with the Vendor Identification register uniquely identifies
any PCI device. Writes to this register have no effect.
Table 35-45. Offset 02h: DID: Device Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: 02h
Offset End: 03h
Size: 16 bit
Default: 503Eh
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
DID
Device Identification Number: This is a 16-bit value
assigned to the GCU device.
Sticky
Bit Reset
Value
Bit Access
503E
RO
35.8.1.3 Offset 04h: PCICMD – Device Command Register
Table 35-46. Offset 04h: PCICMD: Device Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 11
10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
INTD
FBTB
SER
Reserved
PER
VPS
MWE
SS
BM
MEM
IO
Reserved
Interrupt Disable: Setting this bit disables generation of
interrupts by the GCU.
Fast Back-to-Back Enable: This bit is not implemented in
the GCU and is hardwired to 0.
SERR# Enable: This bit is not implemented in the GCU
and is hardwired to 0. The EP80579 uses signals for errors.
Reserved
Parity Error Enable: This bit is not implemented in the
GCU and is hardwired to 0. The EP80579 uses signals for
errors.
VGA Palette Snoop Enable: This bit is not implemented
in the GCU and is hardwired to 0.
Memory Write and Invalidate Enable: This bit is not
implemented in the GCU and is hardwired to 0.
Special Cycle Enable: This bit is not implemented in the
GCU and is hardwired to 0.
Bus Master Enable: This bit is not implemented in the
GCU and is hardwired to 0. GCU cannot be a bus master.
Memory Space Enable: Setting this bit enables access to
the memory regions the device claims through its BARs.
I/O Space Enable: The device does not implement this
functionality since it claims no I/O regions. The bit is
hardwired to 0.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RO
RO
RO
RV
RO
RO
RO
RO
RO
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1266
August 2009
Order Number: 320066-003US