EP80579 Datasheet, PDF (499/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.57 Offset ECh: DERRINJCTL - DRAM Error Injection Control Register
This register controls the IMCH handling of errors on incoming data streams into the
IMCH core from the DRAM interface. This register enables the injection of parity errors
on incoming data streams into the core. The lower 16 bits are the corresponding flip
parity bits for the cacheline of data. The upper bits in the register are for the use and
control of the associated flip parity bits.
The “flip on next data transfer (bit 16)” feature is not supported in the the memory
controller.
DERRINJCTL is used to inject parity errors into the data returned to MCH during data
reads. The other complementary function, ECCDIAG is used to inject parity errors into
DDR upon data writes.
Table 16-111.Offset ECh: DERRINJCTL - DRAM Error Injection Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: ECh
Offset End: EFh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :19
18
17
16
15 :00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
ENDP
Enable/Disable data poisoning for incoming data:
This bit controls whether or not the IMCH marks data as
“poisoned” when a parity error is detected on incoming
data from the DRAM I/F.
0 = Errors are not propagated, only good internal parity
generated.
N
1 = Error Poisoning Enabled. Incoming data with parity
errors are marked as “poisoned” before being sent on
towards its destination when in either 72-bit ECC mode
via the DRC register. Error Injection is possible
regardless of this bit setting. DEFAULTS TO DISABLED.
Enable/Disable parity bits: Flip the designated parity
FLIPADT
bits (bits 15:00) on all data transfers into the core.
If a cacheline is in progress when this register is written,
N
wait until the start of the next cacheline to flip parity bits.
Reserved Reserved
N
Two bits of parity for each 64bits of data. 16 bits of
parity for a cacheline.
FLIPBITS
If the parity error injection is enabled, via setting ENDP
and FLIPADT, the parity bits sent back to MCH along with
N
the cache line read data will be exclusive-or’ed with the
value in this FLIPBITS register
Bit Reset
Value
00h
0b
0b
0b
0000h
Bit Access
RO
RW
RW
RO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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