EP80579 Datasheet, PDF (339/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

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(That is, the limited MSI functionality described here is dedicated to the EDMA
channel.) This second mechanism is preferred for interrupt signaling, but is only
available in platforms running an MSI-capable operating system.
Selection between these two mechanisms is automatic in the IMCH. If MSI messaging
is enabled, as indicated by the enable bit in the MSI control register, then the MSI
interrupt mechanism is used. If MSI message generation is disabled, any initiated
interrupt will use the dedicated pin legacy mechanism.
For both interrupt mechanisms, the interrupt service routine (ISR) must service all
interrupts for all channels. The memory-mapped EDMA Controller Global Status
Register must be statused before returning from the ISR to ensure no additional
interrupts have occurred. Failure to address interrupts in all channels will result in
potential system starvation.
12.10.2
Message Signaled Interrupt (MSI)
The EDMA controller is capable of generating upstream interrupt messages (MSI)
directly to the IA-32 core. An MSI is signaled via a Memory Write to address
0FEEx_xxxxh.
Three 32-bit registers are required in the controller to support this mechanism. The
default values of these registers are compatible with the default value of the IOxAPIC
specification. The three registers are the MSI Control Register (MSICR), MSI Address
Register (MSIAR), and MSI Data Register (MSIDR). Software must program these
registers to appropriate values prior to enabling internal MSI functionality.
Note:
It is unsafe to enable the integrated MSI APIC function of the controller in
environments under control of a non MSI-capable operating system.
The MSI mechanism supports differentiation between interrupts generated during
normal operation (EOT, EOC, stop, and suspend) and interrupts due to errors (abort).
This extra level of granularity is unavailable via the legacy interrupt mechanism.
To facilitate use of a single device driver for the entire EDMA function, a single MSI
register set services all channels. The support for two different messages on behalf of
the controller is included in the MSI register set. Refer to “EDMA Registers: Bus 0,
Device 1, Function 0” on page 501 for the format of these registers.
Note:
The integrated APIC functionality will not support level-sensitive interrupt emulation
requiring the use of broadcast EOI cycles from the FSB. No path is provided to handle
such traffic from IA-32 core to EDMA control engine. Thus the only supported MSI type
is the edge-triggered variety.
The following subsections describe the register set for MSI support.
12.10.2.1 MSI Control Register – MSICR
The MSI Control Register (MSICR) contains control information for MSI interrupt
capability. The multiple-message enable field and MSI enable are contained in this
register.
12.10.2.2 MSI Address Register – MSIAR
The MSI Address Register (MSIAR) contains address information specifying the
message destination address for MSI interrupts.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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