EP80579 Datasheet, PDF (213/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.10
SATA Controller: Bus 0, Device 31, Function 2
The SATA controller includes the registers listed in Table 7-27, Table 7-28, and
Table 7-29. These registers materialize in PCI configuration, I/O, and memory spaces
(via PCI I/O and memory BARs). See Chapter 23.0, “SATA: Bus 0, Device 31, Function
2” for detailed discussion of these registers.
Table 7-27. Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
04h
06h
08h
0Ah
0Dh
10h
14h
18h
1Ch
20h
24h
2Ch
34h
3Ch
40h
44h
48h
4Ah
54h
70h
72h
74h
80h
82h
84h
88h
90h
03h
05h
07h
08h
0Bh
0Dh
13h
17h
1Bh
1Fh
23h
27h
2Fh
34h
3Dh
41h
44h
48h
4Bh
57h
71h
73h
77h
81h
83h
87h
89h
90h
“Offset 00h: ID – Identifiers Register” on page 819
Variable
“Offset 04h: CMD - Command Register” on page 819
0000h
“Offset 06h: STS - Device Status Register” on page 820
02B0h
“Offset 08h: RID - Revision ID Register” on page 821
Variable
“Offset 0Ah: CC - Class Code Register” on page 823
Variable
“Offset 0Dh: MLT – Master Latency Timer Register” on page 823
00h
“Offset 10h: PCMDBA – Primary Command Block Base Address Register” on
page 824
00000001h
“Offset 14h: PCTLBA – Primary Control Block Base Address Register” on page 824 00000001h
“Offset 18h: SCMDBA – Secondary Command Block Base Address Register” on
page 825
00000001h
“Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register” on
page 825
00000001h
“Offset 20h: LBAR – Legacy Bus Master Base Address Register when SCC is SATA
with AHCI PI” on page 826
00000001h
“Offset 24h: ABAR – AHCI Base Address Register” on page 826
00000000h
“Offset 2Ch: SS - Sub System Identifiers Register” on page 827
00000000h
“Offset 34h: CAP – Capabilities Pointer Register” on page 827
80h
“Offset 3Ch: INTR - Interrupt Information Register” on page 828
Variable
“Offset 40h: PTIM – Primary Timing Register” on page 829
0000h
“Offset 44h: D1TIM – Device 1 IDE Timing Register” on page 830
00h
“Offset 48h: SYNCC – Synchronous DMA Control Register” on page 831
00h
“Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register” on page 832
0000h
“Offset 54h: IIOC – IDE I/O Configuration Register” on page 833
00000000h
“Offset 70h: PID – PCI Power Management Capability ID Register” on page 834 Variable
“Offset 72h: PC – PCI Power Management Capabilities Register” on page 834
4002h
“Offset 74h: PMCS – PCI Power Management Control And Status Register” on
page 835
0000h
“Offset 80h: MID – Message Signaled Interrupt Identifiers Register” on page 836 7005h
“Offset 82h: MC – Message Signaled Interrupt Message Control Register” on
page 837
0000h
“Offset 84h: MA – Message Signaled Interrupt Message Address Register” on
page 838
00000000h
“Offset 88h: MD – Message Signaled Interrupt Message Data Register” on
page 838
0000h
“Offset 90h: MAP – Port Mapping Register” on page 839
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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