EP80579 Datasheet, PDF (1593/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6.1.7
Note:
Offset 00000020h: TxMessageControl[0-7] - Transmit Message
Control and Command
These registers are implemented in the SRAM which does not have the capability to
mask writes to reserved bits. Therefore, reserved bits in this CSR will be RW. Software
should treat these bits as reserved and not change the reset value of these bits.
Note:
These registers are implemented in SRAM which is not initialized at power-up or upon
reset. So before enabling the CAN, software needs to update these CSR’s with the reset
values.
Table 39-12. Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
Command (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
00000020h
Offset Start: at 10h
Offset End: 00000023h
at 10h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
00000020h
Offset Start: at 10h
Offset End: 00000023h
at 10h
Size: 32 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range
31 :24
23
22
21
20
19 :16
15 :04
03
Bit Acronym
Bit Description
Sticky
RSVD
Reserved.
WPN_21_16
Write Protect Not. Using the WPN flag enables simple
retransmission of the same message by only having to set
the TRX flag without taking care of the special flags.
‘0’: Bit [21:16] remain unchanged.
‘1’: Bit [21:16] are modified, default.
NOTE: The readback state of this bit is undefined.
RSVD
Reserved.
RTR
Remote Bit
‘0’: This is a standard message
‘1’: This is an RTR message
Extended identifier bit.
IDE
‘0’: This is a standard format message
‘1’: This is an extended format message
DLC
Data Length Code. Invalid values are transmitted as they
are, but only the number of data bytes is limited to eight.
0: Message has 0 data byte, data[63:0] is not used
1: Message has 1 data byte, data [63:56] is used
....
8: Message has 8 data bytes, data [63:0] is used
9-15: Message has 8 data bytes
RSVD
Reserved.
WPN_2
Message Control:
WPN: Write Protect Not
‘0’: Bit [2] remain unchanged.
‘1’: Bit [2] is modified, default.
NOTE: The readback state of this bit is undefined.
Bit Reset
Value
Xh
Xh
Xh
Xh
Xh
Xh
Xh
Xh
Bit Access
RW
RW
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1593