EP80579 Datasheet, PDF (463/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-71. Offset 54h: NSI_SMICMD: NSI SMI Command Register (Sheet 3 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 54h
Offset End: 57h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
08
07
06
05
04 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
FEMR_SMI
NEMR_SMI
CEMR_SMI
Reserved
PED_SMI
Reserved
LD_SMI
Reserved
Generate SMI for NSI Error 7: Generate SMI whenever
bit 6 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Generate SMI for NSI Error 6: Generate SMI whenever
bit 6 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Generate SMI for NSI Error 5: Generate SMI whenever
bit 5 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved
Generate SMI for NSI Error 2: Generate SMI whenever
bit 2 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved
Generate SMI for NSI Error 0: Generate SMI whenever
bit 0 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
463