EP80579 Datasheet, PDF (1065/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-17. Offset 28h: GPE0_STS - General Purpose Event 0 Status Register (Sheet 3 of
4)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 28h
Offset End: 28h
Size: 32 bit
Default: 00000000h
Power Well: Resume
Bit Range
09
Bit Acronym
Bit Description
Sticky
0 = Software clears this bit by writing a 1 to it.
1 = Set to 1 by hardware to indicate that:
• The PME event message was received on one or
more of the PCI Express* Ports
PCI_EXP_STS
• An Assert PMEGPE message received from the
IMCH via NSI
Notes:
1.
Software attempts to clear this bit by writing a
1 to this bit position. If the PCI_EXP_STS bit
went active due to an Assert PMEGPE message,
then a Deassert PMEGPE message must be
received prior to the software write in order for
the bit to be cleared.
2.
If the bit is not cleared and the corresponding
PCI_EXP_EN bit is set, the level-triggered SCI
will remain active.
3.
A race condition exists where the PCI Express*
device sends another PME message because
the PCI Express* device was not serviced
within the time when it must resend the
message. This may result in a spurious
interrupt, and this is comprehended and
approved by the PCI Express* Specification.
The window for this race condition is
approximately 95-105 ms.
Bit Reset
Value
0h
Bit Access
RWC
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes
08
RI_STS
active.
The value of this bit is maintained through a G3 state.
0 = Wake event not caused by the SMBus logic.
1 = Set by hardware to indicate that the wake event
was caused by the SMBus logic.
Note:
1.
If SMB_WAK_STS is set due to SMBus slave
receiving a message, it will be cleared by
internal logic when CPUTHRMTRIP event
happens or by a Power Button Override event.
However, CPUTHRMTRIP or Power Button
override event will not clear SMB_WAK_STS if it
was set due to SMBALERT# signal going active.
07
SMB_WAK_STS 2.
The SMBus controller will independently cause
an SMI# so this bit does not need to do so
(unlike the other bits in this register).
3.
This bit is set by the SMBus slave command
01h (Wake/SMI#) even when the system is in
the S0 state. Therefore, to avoid an instant
wake on subsequent transitions to sleep states,
software must clear this bit after each reception
of the Wake/SMI# command or just prior to
entering the sleep state.
4.
The SMBALERT_STS bit (D31:F3:I/O Offset
00h:bit 5) must be cleared by software before
clearing this bit.
0h
RWC
0h
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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