EP80579 Datasheet, PDF (359/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
14.0 RAS Features and Exception Handling
CMI is designed to bring enterprise level reliability, availability, serviceability, usability,
and manageability (RASUM) to the embedded platform.
14.1
RAS Features
14.1.1
14.1.1.1
14.1.1.2
14.1.1.3
Data Protection
Due to the nature of having various data protection schemes on the different interfaces
(ECC, parity, and CRC) it is necessary to be able to convert between them when
transferring data internally. To accomplish this, protection of internal data is done with
parity.
DRAM ECC
The DRAM interface uses a standard SEC/DED ECC across a 64-bit data quantity.
PCI Express Interface
These high-speed serial interfaces have traditional CRC protection. The data packets
utilize a 32-bit CRC protection scheme, specifically the same CRC-32 used by Ethernet
- 0x04C11DB7. The smaller and less error-prone link packets utilize a 16-bit CRC
scheme. Since packets utilize 8B/10B encoding and not all encodings are used, this
provides further data protection because illegal codes can be detected. Also, if errors
are detected on the reception of data packets due to various transients, these data
packets can be retransmitted. Hardware logic supports this link-level retry without
software intervention.
Data Error Propagation Between Interfaces/Units
Due to the nature of having various data protection schemes; ECC, parity, and CRC - it
is necessary to be able to convert between the separate schemes. Beyond this
requirement, it is necessary to indicate whether or not incoming data is corrupted.
Also, it is useful to know when internal data has been corrupted during transit. To
accomplish this, the IMCH uses parity to protect internal data. This requires units to
add two parity bits for each 64 bits of data path width. Data received by a unit from
outside the chip creates two parity bits to travel with the data, one provides parity on
the upper 32 bits, and the other provides parity on the lower 32 bits. If either of the
32-bit halves is required to be poisoned, both halves are poisoned. This provides the
user of the data a mechanism to recognize when a bit was flipped in transit by
detecting when only one of the parity bits is bad. The user will flag this error condition
as well as mark both halves bad. This covers both cases of the data starting out as
either good or bad. If it started out as good, but a bit was flipped, it is indeed corrupted
and must be marked as such. In the case where it started out as bad, and a bit was
flipped, it is still corrupted, although probably a different data value than its starting
value. This scheme works when all quantities being passed are 64 bits or greater. If a
data path must be padded, it must be padded with zeroes. Even parity will be used for
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
359