EP80579 Datasheet, PDF (470/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.22 Offset 64h: FSB_EMASK - FSB Error Mask Register
This register masks the FSB unit errors from being recognized, preventing them from
being logged at the unit or global level, and no interrupt/messages are generated.
These bits are sticky through reset.
Table 16-76. Offset 64h: FSB_EMASK - FSB Error Mask Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 64h
Offset End: 65h
Size: 16 bit
Default: 0009h
Power Well: Core
Bit Range
15 : 10
09 06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
Reserved Reserved
Y
Non-DRAM Lock Error Mask: This bit is sticky through
reset.
NDLOCKM _{0 = Enable Non-DRAM Lock Error detection and reporting}
Y
1 = Mask Non-DRAM Lock Error detection and reporting
ATOMM
FSB Address Above TOM Mask: This bit is sticky through
reset.
0 = Enable FSB address above TOM detection and
Y
reporting
1 = Mask address above TOM detection and reporting
Reserved Reserved
Y
FSB Address Strobe Glitch Detected Mask: This bit is
sticky through reset.
FSBAGLM 0 = Enable FSB address strobe glitch detection and
Y
reporting
1 = Mask address strobe glitch detection and reporting
FSB Data Strobe Glitch Detected Mask: This bit is
sticky through reset.
FSBDGLM _{0 = Enable FSB data strobe glitch detection and reporting}
Y
1 = Mask data strobe glitch detection and reporting
Reserved Reserved
Y
Bit Reset
Value
00h
0000b
0b
0b
1b
0b
0b
1b
Bit Access
RW
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
470
August 2009
Order Number: 320066-003US