EP80579 Datasheet, PDF (646/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.65 Offset 284h: WL_CNTL[4:0] - Write Levelization[4:0] Control Register
This register controls functionality of Write Levelization (WL). The EP80579 implements
5 CSR’s to control WL. The mapping of each of these CSR’s to the byte lane is shown in
Table 16-292.
.
Table 16-292.Mapping of DQ and DQS/# byte lanes to WL_CNTL[4:0] CSR’s
CSR Name
Byte 0
DQS/#[0]
DQ[7:0]
Byte 1
DQS/#[1]
DQ[15:8]
Byte 2
DQS/#[2]
DQ[23:16]
Byte 3
DQS/#[0]
DQ[31:24]
Byte 4
DQS/#[0]
DQ[39:32]
Byte 5
DQS/#[0]
DQ[47:40]
Byte 6
DQS/#[6]
DQ[55:48]
Byte 7
DQS/#[7]
DQ[63:56]
Byte 8
DQS/#[8]
DQ[71:64]
WL_CNTL CSR #
WL_CNTL[0]
Generate DQS/# Pulse
[CSR bits]
Latch DQ Feedback
Data [CSR bits]
ODD_DRV_WL_PULSE
ODD_WL_DATA[7:0]
EVEN_DR_WL_PULSE
EVEN_WL_DATA[7:0]
WL_CNTL[1]
ODD_DRV_WL_PULSE
ODD_WL_DATA[7:0]
EVEN_DR_WL_PULSE
EVEN_WL_DATA[7:0]
WL_CNTL[2]
ODD_DRV_WL_PULSE
ODD_WL_DATA[7:0]
EVEN_DR_WL_PULSE
EVEN_WL_DATA[7:0]
WL_CNTL[3]
ODD_DRV_WL_PULSE
ODD_WL_DATA[7:0]
EVEN_DR_WL_PULSE
EVEN_WL_DATA[7:0]
WL_CNTL[4]
ODD_DRV_WL_PULSE
ODD_WL_DATA[7:0]
This CSR is in the memory-mapped IO region of Bus 0, Device 0, Function 0 of the
memory controller. The SMRBASE register described in Section 16.1.1.9, “Offset 14h:
SMRBASE - System Memory RCOMP Base Address Register” on page 395, provides the
base address for these registers. The offsets listed for the following registers are
relative to this base address.
The value for BAR for all registers in this section is BAR14h.
Intel^® EP80579 Integrated Processor Product Line Datasheet
646
August 2009
Order Number: 320066-003US