EP80579 Datasheet, PDF (1201/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.6.2.11 Offset 18h: WDTLR - WDT Lock Register
Table 33-36. Offset 18h: WDTLR - WDT Lock Register
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 18h
Offset End: 18h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
WDT Timeout Configuration: This register is used to
choose the functionality of the timer.
0 = Watchdog Timer Mode: When enabled (i.e.
WDT_ENABLE goes from ‘0’ to ‘1’) the timer reloads
Preload Value 1 and start decrementing. (Default)
Upon reaching the second stage timeout the
WDT_TOUT# is driven low once and does not change
again until Power is cycled or a hard reset occurs.
WDT_TOUT_CN 1 = Free Running Mode: WDT_TOUT# changes from
F
previous state when the next timeout occurs. The
timer ignores the first stage. The timer only uses
Preload Value 2. In this mode the timer is restarted
whenever WDT_ENABLE goes from a 0 to a 1. This
means that the timer reloads Preload Value 2 and
start decrementing every time it is enabled.
In free running mode it is not necessary to reload the
timer as it is done automatically every time the
descrementer reaches zero.
WDT_ENABLE
Watchdog Timer Enable: The following bit enables or
disables the WDT.
0 = Disabled (Default)
1 = Enabled
Note: This bit cannot be modified if WDT_LOCK has
been set.
Note: In free-running mode Preload Value 2 is reloaded
into the down counter every time WDT_ENABLE
goes from ‘0’ to ‘1’.
Note: In WDT mode Preload Value 1 is reloaded every
time WDT_ENABLE goes from ‘0’ to ‘1’ or the
WDT_RELOAD bit is written using the proper
sequence of writes (See Register Unlocking
Sequence). When the WDT second stage timeout
occurs, a reset must happen.
Note: Software must guarantee that a timeout is not
about to occur before disabling the timer. A reload
sequence is suggested.
WDT_LOCK
Watchdog Timer Lock: Setting this bit locks the values
of this register until a hard-reset occurs or power is
cycled.
0 = Unlocked (Default)
1 = Locked
Note: Writing a “0” has no effect on this bit. Write is
only allowed from “0” to “1” once. It cannot be
changed until either power is cycled or a hard-
reset occurs.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RW
RW
RWL
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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