EP80579 Datasheet, PDF (341/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• For either case, the likely software response to the interrupt will be a posted write
“door-bell” access to a memory mapped control register in the EDMA destination
device to communicate completion of the transfer. (Semantic: EDMA transfer
completed without errors, you have all the data, GO.)
• In the absence of internal interlocks as described above, multiple failures are
possible. The APIC message could bypass EDMA data pending within the inbound/
outbound arbiter, and the IA-32 core doorbell write could do the same. This would
result in stale data “executed” in response to the doorbell.
The internal IMCH hardware interlock prevents APIC messages from being forwarded to
the FSB while posted data remains pending in the inbound/outbound arbiter. This
prevents most of the problematic behavior in this case. If the APIC is disabled, the IA-
32 core must retrieve the interrupt vector from the 8259 emulator, and the read
completion interlock will then guarantee that all posted write data has cleared the
arbiter.
Another potential issue is relaxed write ordering within a system agent en route to the
EDMA destination device. If the hardware were to issue EDMA outbound posted writes
and IA-32 core posted writes with differing stream ID codes, an intermediary
component may allow the IA-32 core doorbell access to move around posted EDMA
data. This would again result in stale data “executed” by the destination device.
The IMCH could solve this problem by issuing an explicit FENCE between the final EDMA
write and the interrupt, preventing subsequent IA-32 core accesses from reordering en
route to the destination. A simpler (but more limited) solution is to utilize the same
stream ID for all outbound traffic regardless of source. This makes transactions
initiated by each EDMA channel indistinguishable from those initiated by any of the IA-
32 core threads. With no stream ID information to determine reordering legality, an
intermediary device must necessarily enforce strong ordering for all accesses
outbound.
The single initiator ID in concert with the internal interlock for APIC messages and read
completions is sufficient to guarantee proper behavior. The implementation guarantees
that any flag write or data read to the destination port will necessarily push the EDMA
transfer data ahead of it, ensuring correct producer/consumer operation.
12.11
Initiating an EDMA Transfer
The following subsections detail the steps the software must take in programming a
channel to initiate a transfer (or chain of transfers). The steps covered include channel
initialization, transfer start, and suspend or stop. Each channel is designed to have
independent control of interrupt enabling and generation, and independent transfer
attribute controls; this provides the greatest flexibility to the application program.
12.11.1
Setup and Initiation
Initializing a channel begins with constructing one or more chain descriptors in local
system memory. Each chain descriptor takes the form described in Section 12.3.1,
“Chain Descriptor Definition” on page 311. Once the descriptors are defined, the
following steps are required to initiate a transfer:
1. Ensure the EDMA channel is enabled and in Normal Mode by setting the EDMA
Enable and Mode bits of the EDMA Control Register.
2. The channel must be inactive/idle prior to starting a transfer. This may be verified
by reading the Channel Active bit in the Channel Status Register (CSR), which is
clear when the channel is inactive/idle.
3. Update the Next Descriptor Address Register (NDAR/NDUAR) with the address of
the first chain descriptor in local system memory.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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