EP80579 Datasheet, PDF (1160/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 32-6. Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register
(Sheet 2 of 3)
Description:
Timer 0:
+ 107h
100 – 107h, Timer 1:
120 – 127h, Timer 2:
140 – 147h, Timer n:
(20h * n) +100h
-
(20h * n)
View: IA F
Base Address: HPTC
Offset Start: 100h at 20h
Offset End: 107h at 20h
Size: 64 bit
Default: Xh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
13 :09
Interrupt Route: (where n is the timer number: 00 to
31). This 5-bit field indicates the routing for the interrupt
to the I/O APIC. A maximum value of 32 interrupts is
supported. The default is 00h. Software writes to this field
to select which interrupt in the I/O (x)APIC used for this
timer’s interrupt. If the value is not supported by this
particular timer, then the value read back does not match
what is written. The software must only write valid values.
Notes:
TIMERn_INT_R ^1.
OUT_CNF
If the Legacy Replacement Rout bit is set, then
Timers 0 and 1 have a different routing, and this
bit field has no effect for those two timers.
2.
Timer 0,1: The software is responsible to make
sure it programs a valid value (decimal 20, 21,
22, or 23) for this field. The logic does not check
the validity of the value written.
3.
Timer 2: The software is responsible to make sure
it programs a valid value (decimal 11, 20, 21, 22,
or 23) for this field. The logic does not check the
validity of the value written.
Xh
RW
0 = Timer n 32-bit Mode: (where n is the timer
number: 00 to 31). Software can set this bit to force
a 64-bit timer to behave as a 32-bit timer. Timer 0:
08
TIMERn_32MOD
E_CNF
1=
Bit is read/write and defaults to 0.64 bit
32 bit
Timers 1 and 2: Hardwired to 0. Writes have no effect
(since these two timers are 32 bits).
Xh
RW or RO
07
Reserved Reserved:
0b
RO
Timer n Value Set: Software uses this bit only for timers
that have been set to periodic mode.
0 = Disabled. Software does NOT have to write this bit
back to 0 (it automatically clears).
06
TIMERn_VAL_S
ET_CNF
1 = By writing this bit to a 1, the software is allowed to
directly set the timer’s accumulator.
Note: Software must not write a 1 to this bit position if
the timer is set to non-periodic mode.
Note: This bit returns zero when read. Writes will only
have an effect for Timer 0 if it is set to periodic
mode. Writes have no effect for Timers 1 and 2.
Xh
RW or RO
Timer n Size: (where n is the timer number: 00 to 31).
This read-only field indicates the size of the timer.
05
TIMERn_ ^{0 = 32 bits}
SIZE_CAP 1 = 64 bits
Timer 0: Value is 1 (64 bits).
Timers 1 and 2: Value is 0 (32 bits).
Xh
RO
Periodic Interrupt Capable: (where n is the timer
number: 00 to 31). If this read-only bit is 1, then the
TIMERn_ ^{hardware supports a periodic mode for this timer’s}
04
PER_INT_ ^interrupt.
CAP
Timer 0: Hardwired to 1 (supports the periodic interrupt).
Timers 1 and 2: Hardwired to 0 (does not support periodic
interrupts), so the bit is always read as zero.
Xh
RO
Note: Reads or writes to unimplemented timers must not be attempted. Reads from any unimplemented registers return an
undetermined value.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1160
August 2009
Order Number: 320066-003US