EP80579 Datasheet, PDF (1153/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.0
Note:
32.1
Note:
32.2
High Precision Event Timers
This section documents the CMI-specific behavior and the generic HPET (High Precision
Event Timers) Specification, Revision 1.0a.
Overview
This function provides a set of timers that can be used by the operating system. The
timers are defined such that in the future, the OS may be able to assign specific timers
to be used directly by specific applications. Each timer can be configured to cause a
separate interrupt. This specification allows for a block of 32 timers, with support for up
to eight blocks, for a total of 256 timers. The timers are implemented as a single
counter with a set of comparators. The counter increases monotonically. Each timer
includes a value register and a comparator. Each individual timer can generate an
interrupt when the value in its value register matches value in the main counter. Some
of the timers can be enabled to generate a periodic interrupt.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; However, the BIOS sets this space prior to
handing it over to the OS. It is not expected that the OS move the location of these
timers once they are set by the BIOS.
For additional information see Section 1.3, “Referenced Documents and Related
Websites”.
Register Details
The timer registers are memory mapped in a non-indexed scheme. This allows the CPU
to directly access each register without having to use an index register. The timer
register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries.
General Behavioral Rules:
• Software must not attempt to read or write across register boundaries. For
example, a 32-bit access must be to offset x0h, x4h, x8h, or xCh.
• 32-bit accesses must not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh,
0Eh, or 0Fh. Any accesses to these offsets results in an unexpected behavior and
may result in a master abort. However, these accesses may not result in system
hangs.
• 64-bit accesses can only be to x0h and must not cross 64-bit boundaries.
• Software must not write to read-only registers.
• Software must not expect any particular or consistent value when reading reserved
registers or bits.
• The timer register space is memory mapped to a 1 K block.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1153