EP80579 Datasheet, PDF (1082/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.5.3.2 C0→C2 Entry Sequence
Table 27-29. C0→C2→C0 Timings
Sym
Min
Max
Units
Description
T1
0
Note 1
CPU Interface Signals Latched prior to STPCLK# active. Note that this
does not apply for synchronous SMI's. Changed as per DCN #014, part 1.
T2a
0
Note 2
STPCLK# active to Stop-Grant cycle on processor front-side bus (can wait
forever)
T2b
0
Note 3
Stop-Grant on FSB to Stop-Grant on NSI.
Note: This is according to an IMCH specification.
T3a
0
Note 1
Stop-Grant on NSI to Go-C2 message. This must be as short as feasible.
T3b
128
Note 3
BCLK
Go C-2 message to Ack-C2 message. Note that this is according to an
IMCH specification and is only required if the IMCH has the CPULSLP#
signal. It is needed to enforce the Stop-Grant to CPUSLP# timing
requirements. If the IMCH does not have the CPUSLP# signal, then this
can be 0.
T4a
0
8
PCI CLK
Break Event to when GO_C0 message is ready to be sent. The actual
message may be delayed if NSI is busy with other traffic.
T4b
0
Note 3
Go-C0 message to Ack-C0 message. Note that this is an IMCH
specification. This must be as short as feasible.
T5
0
Note 1
End of Ack_C0 message to STPCLK# high
T6
8
9
PCI CLK
STPCLK# high to processor interface signals unlatched.
1.
This value must be small (a few PCI clocks). For messages, it may be difficult to determine the maximum time, since
power management messages may have to wait for other traffic on NSI.
2.
This is a processor specification that is unbounded.
3.
This is an IMCH specification. The maximum is presently not specified. CMI should not be dependent on this specific
value.
The processor goes from a C0 to a C2 state because all of the threads in the processor
are idle and have nothing to do. The decision to go to the C2 state is made by software.
The following timings are shown in Figure 27-1.
1. The processor reads the Level 2 register.
2. t1 prior to asserting STPCLK#, CMI will latch the processor interface signals, except
SMI# activation due to a synchronous SMI event. Changed as per DCN #014, part
3.
3. t2a later, in response to observing STPCLK# active, the processor(s) performs one
or more Stop-Grant cycles on the front-side bus.
4. t2b later, IMCH forwards the last Stop-Grant cycle to CMI via NSI. This will be called
“REQ-C2.”
5. The processor is now in C2 state. There are some additional steps below that must
complete between the IICH and IMCH to keep them in synchronization.
6. t3a after receiving the Stop-Grant from the IMCH, the IICH sends a Go-C2 message
to the IMCH
7. t3b after receiving the Go-C2 message, the IMCH sends an Ack-C2 message. At
this point, the IMCH is permitted to send the REQ-C0 (Break-Ind) message.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1082
August 2009
Order Number: 320066-003US