EP80579 Datasheet, PDF (720/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.2.2.6 Offset 08h: TCTL1 - TCO 1 Control Register
Table 18-7. Offset 08h: TCTL1 - TCO 1 Control Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 08h
Offset End: 09h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 13
12
11
10
Bit Acronym
Bit Description
Sticky
Reserved Reserved
TCO_LOCK
0 = A core well reset is required to change this bit from
1 to 0. This bit defaults to 0.
1 = This bit prevents writes from changing the TCO_EN
bit (in offset 30h of Power Management I/O space).
Once this bit is set to 1, it can not be cleared by
software writing a 0 to this bit location.
TCO_TMR_
HALT
0 = The TCO timer is enabled to count.
1 = The TCO Timer halts. It does not count, and thus
cannot reach a value that causes an SMI# or set
the SECOND_TO_STS bit. When set, this bit
prevents rebooting.
SEND_NOW
0 = Clears this bit when it has completed sending the
message. Warning: Software must not set this bit
to 1 again until the CMI has set it back to 0.
1 = Set the SEND_NOW bit and causes the LAN
controller to reset, which can have unpredictable
side-effects. Unless software protects against these
side-effects, software must not set or otherwise
use the SEND_NOW bit.
0 = Normal NMI functionality
1 = Setting this bit 1 forces all NMIs to instead cause
an SMI#, and is reported in the TCO1_STS register.
NMI2SMI_EN bit is set AND the NMI_EN bit is set,
the NMI# is routed to cause an SMI#. No NMI is
caused. However, if the GBL_SMI_EN bit is not set,
then no SMI# is generated, either. If NMI2SMI_EN
is set but the NMI_EN bit is not set, then no NMI or
SMI# is generated. The following table shows the
possible combinations:
Bit Reset
Value
000h
0h
0h
0h
Bit Access
RO
RW
RW
RW
09
NMI2SMI_EN
NMI_EN
GBL_SMI
_EN
Description
0b
0b
No SMI# at all because
GBL_SMI_EN = 0
0b
1b
SMI# is caused due to NMI events
1b
0b
No SMI# at all because
GBL_SMI_EN = 0
1b
1b
No SMI# due to NMI because
NMI_EN = 1
0h
RW
08
07 : 00
NMI_NOW
Reserved
0 = Software clears this bit by writing a 1 to it. The NMI
handler is expected to clear this bit. Another NMI is
not generated until the bit is cleared.
1 = Writing a 1 to this bit causes an NMI. This allows
the BIOS or SMI handler to force an entry to the
NMI handler.
Reserved
0h
RWC
00h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
720
August 2009
Order Number: 320066-003US