EP80579 Datasheet, PDF (354/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.6
• Device 0, Function 0: Critical DRAM control registers, a portion of DRC, DRT clock
gearing and clock disable registers
• Device 0, Function 0: ECO sticky register
• Device 0, Function 0, Bar 14: BIOS notepad sticky register
• Device 0, Function 1: error information registers (Not the command registers)
• Device 2, Function 0: error information registers (Not the command registers)
• Device 3, Function 0: error information registers (Not the command registers)
• Device 8, Function 0: PILOT control registers
• Device 8 Function 0: Power On Configuration bits
IMCH I/O Mapped Registers
The IMCH contains two registers that reside in the IA-32 core I/O address space − the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
Table 13-2. Summary of IMCH PCI Configuration Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
Default
Value
0CF8h
0CFCh
0CF8h
0CFCh
“Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register” on page 354 00000000h
“Offset 0CFCh: CONFIG_DATA: Configuration Data Register” on page 355
00000000h
13.6.0.1
Offset 0CF8h: CONFIG_ADDRESS - Configuration Address Register
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or
Word reference will “pass through” the Configuration Address Register and NSI onto the
IICH as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent configuration
access is intended.
Table 13-3. Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register (Sheet 1 of
2)
Description:
View: IA F Base Address: 0000h (IO)
Offset Start: 0CF8h
Offset End: 0CF8h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30 :24
23 :16
Bit Acronym
Bit Description
Sticky
CFGE
Configuration Enable.
0 = Accesses to PCI configuration space are disabled.
1 = Accesses to PCI configuration space are enabled.
Reserved Reserved. These bits are read only and have a value of 0.
Bus_Number
Contains the bus number being targeted by the
configuration cycle.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
354
August 2009
Order Number: 320066-003US