EP80579 Datasheet, PDF (1180/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-16. Interrupt Identification Register Decode (Sheet 2 of 2)
0
0
1
0
Third
Highest
0
0
0
0
Fourth
Highest
Transmit
FIFO Data
Request
Modem
Status
Non-FIFO mode: Transmit
Holding Register Empty
FIFO mode: Transmit FIFO has
half or less than half data.
Clear to Send, Data Set Ready,
Ring Indicator, Received Line
Signal Detect
Reading the IIR Register (if the
source of the interrupt) or writing
into the Transmit Holding Register.
Reading the IIR Register (if the
source of the interrupt) or writing
to the Transmitter FIFO.
Reading the modem status register
33.5.3.5
Offset 02h: FCR - FIFO Control Register
FCR is a write-only register that is located at the same address as the IIR (IIR is a
read-only register). FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
Table 33-17. Offset 02h: FCR - FIFO Control Register (Sheet 1 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :06
05 :03
02
Bit Acronym
Bit Description
Sticky
ITL_1_0
Reserved
RESETTF
Interrupt Trigger Level (bits [1:0]): When the
number of bytes in the receiver FIFO equals the
interrupt trigger level programmed into this field and
the Received Data Available Interrupt is enabled (via
IER), an interrupt is generated and appropriate bits are
set in the IIR.
00 1 byte or more in FIFO causes interrupt
01 RSVD
10 8 bytes or more in FIFO causes interrupt
11 RSVD
Reserved. Must be programmed to 0.
Reset transmitter FIFO: When RESETTF is set to 1,
the transmitter FIFO counter logic is set to 0, effectively
clearing all the bytes in the FIFO. The TDRQ bit in LSR
are set and IIR shows a transmitter requests data
interrupt if the TIE bit in the IER register is set. The
transmitter shift register is not cleared; it completes the
current transmission. After the FIFO is cleared, RESETTF
is automatically reset to 0.
0 = Writing 0 has no effect
1 = The transmitter FIFO is cleared (FIFO counter set
to 0). After clearing, bit is automatically reset to 0
Bit Reset
Value
00b
000b
0b
Bit Access
WO
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1180
August 2009
Order Number: 320066-003US