EP80579 Datasheet, PDF (843/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-36. Offset C0h: ATC – APM Trapping Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: C0h
Offset End: C0h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
SPT
PST
PMT
Secondary Master Trap (SPT): Enables trapping and
SMI# assertion on legacy I/O accesses to 170h-177h and
376h. The active device on the secondary interface must
be device 0 for the trap and/or SMI# to occur.
Primary Slave Trap (PST): Enables trapping and SMI#
assertion on legacy I/O accesses to 1F0h-1F7h and 3F6h.
The active device on the primary interface must be device
1 for the trap and/or SMI# to occur.
Primary Master Trap (PMT): Enables trapping and
SMI# assertion on legacy I/O accesses to 1F0h-1F7h and
3F6h. The active device on the primary interface must be
device 0 for the trap and/or SMI# to occur.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
23.1.7.2 Offset C4h: ATS – ATM Trapping Status Register
Table 23-37. Offset C4h: ATS – ATM Trapping Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: C4h
Offset End: C4h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03
02
01
00
Bit Acronym
Bit Description
Reserved
SST
SPT
PST
PMT
Reserved
Secondary Slave Trap (SST): Indicates that a trap
occurred to the secondary slave device.
Secondary Master Trap (SPT): Indicates that a trap
occurred to the secondary master device.
Primary Slave Trap (PST): Indicates that a trap
occurred to the primary slave device.
Primary Master Trap (PMT): Indicates that a trap
occurred to the primary master device.
Sticky
Bit Reset
Value
0h
0h
Bit Access
RO
RWC
0h
RWC
0h
RWC
0h
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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