EP80579 Datasheet, PDF (595/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-216.Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register
(Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 158h
Offset End: 15Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 158h
Offset End: 15Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
Mask SMB Clock Low Timeout Error Detect Mask
This bit is sticky through reset.
MSCLTEDM _{0 = Enable SMB Clock Low Timeout error detection.}
Y
1 = Disable SMB Clock Low Timeout error detection.
Mask Unexpected NAK on SMB Error Detect Mask
This bit is sticky through reset.
MUNSEDM _{0 = Enable Unexpected NAK on SMB error detection.}
Y
1 = Disable Unexpected NAK on SMB error detection.
Mask SMB lost Bus Arbitration Error Detect Mistakes
bit is sticky through reset.
MSLBAEDM _{0 = Enable SMB arbitration loss detection.}
Y
1 = Disable SMB arbitration loss detection.
Bit Reset
Value
0b
0b
0b
Bit Access
RW
RW
RW
16.4.1.78 Offset 160h: PEAFERR - PCI Express* First Error Register
Locks after first error.
Table 16-217.Offset 160h: PEAFERR - PCI Express First Error Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 160h
Offset End: 163h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 160h
Offset End: 163h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 09
08
07
06
Bit Acronym
Bit Description
Sticky
Reserved Reserved
Device Fatal Error Detected [STICKY]: This bit is for
internally detected fatal errors.
DFED
0 = No error detected
Y
1 = Error Detected
Device Non-Fatal Error Detected [STICKY]: This bit is
for internally detected non-fatal errors.
DNFED
0 = No error detected
Y
1 = Error Detected
Device Correctable Error Detected [STICKY]: This bit
is for internally detected correctable errors.
DCED
0 = No error detected
Y
1 = Error Detected
Bit Reset
Value
000000h
0b
0b
0b
Bit Access
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
595