EP80579 Datasheet, PDF (1192/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.5.4.2
FIFO Polled Mode Operation
With the FIFOs enabled (TRFIFOE bit of FCR set to 1), setting IER[3:0] to all zeros puts
the serial port in the FIFO polled mode of operation. Since the receiver and the
transmitter are controlled separately, either one or both can be in the polled mode of
operation. In this mode, software checks receiver and transmitter status via the LSR.
As stated in the register description:
• LSR[0] is set as long as there is one byte in the receiver FIFO.
• LSR[1] through LSR[4] specify which error(s) has occurred for the character at the
top of the FIFO. Character error status is handled the same way as interrupt mode.
The IIR is not affected since IER[2] = 0.
• LSR[5] indicates when the transmitter FIFO needs data.
• LSR[6] indicates that both the transmitter FIFO and shift register are empty.
• LSR[7] indicates whether there are any errors in the receiver FIFO.
33.6
Logical Device 6: Watchdog Timer
33.6.1
Overview
This device is a Watchdog timer that provides a resolution that ranges from 1 µs to 10
minutes. The timer uses a 35-bit down-counter.
The counter is loaded with the value from the 1^st Preload register. The timer is then
enabled and it starts counting down. The time at which the WDT first starts counting
down is called the first stage. If the host fails to reload the WDT before the 35-bit down
counter reaches zero the WDT generates an internal interrupt.
After the interrupt is generated the WDT loads the value from the 2^nd Preload register
into the WDT’s 35-bit Down-Counter and starts counting down. The WDT is now in the
second stage. If the host still fails to reload the WDT before the second timeout, the
WDT drives the WDT_TOUT# pin low and sets the timeout bit (WDT_TIMEOUT). This bit
indicates that the System has become unstable. The WDT_TOUT# pin is held low until
the system is Reset or the WDT times out again (Depends on TOUT_CNF). The process
of reloading the WDT involves the following sequence of writes:
1. Write “80” to offset BAR1 + 0Ch
2. Write “86” to offset BAR1 + 0Ch
3. Write ‘1’ to WDT_RELOAD in Reload Register.
The same process is used for setting the values in the preload registers. The only
difference exists in step 3. Instead of writing a ‘1’ to the WDT_RELOAD, you write the
desired preload value into the corresponding Preload register. This value is not loaded
into the 35-bit down counter until the next time the WDT reenters the stage. For
example, if Preload Value 2 is changed, it is not loaded into the 35-bit down counter
until the next time the WDT enters the second stage.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1192
August 2009
Order Number: 320066-003US