EP80579 Datasheet, PDF (1513/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.16 XOFFRXC – XOFF Received Count Register
This register counts the number of XOFF packets received. XOFF packets can use the
global address or the station address. This register will only increment if the driver has
receives enabled.
Table 37-94. XOFFRXC: XOFF Received Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4050h
Offset End: 4053h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4050h
Offset End: 4053h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4050h
Offset End: 4053h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
XOFFRXC Number of XOFF packets received.
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.17 XOFFTXC – XOFF Transmitted Count Register
This register counts the number of XOFF packets transmitted. These packets can be
either hardware-initiated due to queue fullness, or due to software-initiated action
(using TCTL.SWXOFF). This register will only increment if transmits are enabled.
Table 37-95. XOFFTXC: XOFF Transmitted Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4054h
Offset End: 4057h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4054h
Offset End: 4057h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4054h
Offset End: 4057h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
XOFFTXC Number of XOFF packets transmitted.
Sticky
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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