EP80579 Datasheet, PDF (413/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.27 Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control
Register
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MByte.
Table 16-29. Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Fh
Offset End: 9Fh
Size: 8 bit
Default: 07h
Power Well: Core
Bit Range
07
06 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
E_SMERR
Reserved
SM_CACHE
SM_L1
SM_L2
Invalid SMRAM Access:
0 = CPU has not accessed the defined memory ranges in
Extended SMRAM.
1 = This bit is set when CPU has accessed the defined
memory ranges in Extended SMRAM (High Memory
and T-segment) while not in SMM space and with the
D-OPEN bit = 0. It is software’s responsibility to clear
this bit. This bit is cleared by software writing a 1 to
the bit location.
Reserved
SMRAM Cacheable: This bit is forced to 1 by IMCH.
(Moved from ESMRAMC bit 5)
L1 Cache Enable for SMRAM: This bit is forced to 1 by
IMCH. (Moved from ESMRAMC bit 4)
L2 Cache Enable for SMRAM: This bit is forced to 1 by
IMCH. (Moved from ESMRAMC bit 3)
Bit Reset
Value
0b
0h
1b
1b
1b
Bit Access
RWC
RO
RO
RO
16.1.1.28 Offset B8h: IMCH_MENCBASE - IA/ASU Shared Non-Coherent (AIOC-
Direct) Memory Base Address Register
Table 16-30. Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: B8h
Offset End: BBh
Size: 32 bit
Default: 000FFFFFh
Power Well: Core
Bit Range
31 : 20
19 : 00
Bit Acronym
Bit Description
Sticky
Reserved
MENCBASE
Reserved
IA/ASU Shared Non-Coherent Memory Base Address
Bits[31:12]: Specifies the address of the lower boundary
of the IA/ASU shared non-coherent window in 32-bit
system address space. The window is 4KB-aligned and
inclusive of this address. This register field specifies
bits[31:12] of the address; bits[11:0] are assumed zeros
given 4KB alignment.
Bit Reset
Value
000h
FFFFFh
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
413