EP80579 Datasheet, PDF (1648/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.8 Offset 001Ch: TS_RSysTimeHI - Raw System Time High Register
Register
Name
TS_RSysTimeHI
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RawSystemTime_High[31:0]
Table 41-18. Offset 001Ch: TS_RSysTimeHI Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 0000001Ch
Offset End: 0000001Fh
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 0
This register contains the upper 32 bits of system time.
When you want to read or write the system time, this
register typically first accesses the RawSystemTime_Low
RawSystemTime Register. This register pair contains the raw system timer
_High
value, and no latching of system time occurs when the
lower half is read. Time could increment between the
reading of the lower 32 bits in the RawSystemTime_Low
register and the reading of this register.
Bit Reset
Value
0000h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1648
August 2009
Order Number: 320066-003US