EP80579 Datasheet, PDF (400/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-17. Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 53h
Offset End: 53h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
00
Bit Acronym
Bit Description
Sticky
THRO
Throttled-Read Occurred:
0 = Writing a zero clears this bit.
1 = This bit is set by hardware when a read is throttled.
This happens when the maximum allowed number of
reads has been reached during a time-slice and there
is at least one more read to be done.
Bit Reset
Value
0b
Bit Access
RW0C
16.1.1.16 Offset 58h: FDHC - Fixed DRAM Hole Control Register
This 8-bit register controls a fixed DRAM hole from 15–16 Mbytes.
Table 16-18. Offset 58h: FDHC - Fixed DRAM Hole Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 58h
Offset End: 58h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06 : 00
Bit Acronym
Bit Description
Sticky
HEN
Reserved
Hole Enable: This field enables a memory hole in DRAM
space. The DRAM that lies “behind” this space is not
remapped.
0 = No memory hole
1 = Memory hole from 15–16 Mbytes. Accesses in this
range are sent to NSI.
Reserved
Bit Reset
Value
0b
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
400
August 2009
Order Number: 320066-003US