EP80579 Datasheet, PDF (916/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1.10 Offset 0Dh: AUXC: Auxiliary Control Register
Table 24-28. Offset 0Dh: AUXC: Auxiliary Control Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 0Dh
Offset End: 0Dh
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
E32B
AAC
Reserved
Enable 32-byte Buffer:
0 = The Host Block Data register is a pointer into a
single register.
1 = When set, the Host Block Data register is a pointer
into a 32-byte buffer. This enables the block
commands to transfer or receive up to 32-bytes
before the CMI generates an interrupt.
Automatically Append CRC:
0 = Does not automatically append the CRC
1 = Automatically appends the CRC
This bit must not be changed during SM Bus
transactions, or undetermined behavior results. It
should be programmed only once during the lifetime of
the function.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
24.3.1.11 Offset 0Eh: SMLC: SMLINK_PIN_CTL Register
This register is only applicable in the TCO compatible mode.
This register is in the resume well and is reset by CF9 RESET or RSMRST#.
Table 24-29. Offset 0Eh: SMLC: SMLINK_PIN_CTL Register (Sheet 1 of 2)
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 07h
Bus:Device:Function: 0:31:3
Offset Start: 0Eh
Offset End: 0Eh
Power Well: Resume^a
Bit Range
07 : 03
02
01
Bit Acronym
Bit Description
Sticky
Reserved Reserved
This read/write bit has a default of 1.
0 = Drives the SMLINK[0] pin low, independent of what
SMLINK_CLK_C
TL
the other SMLINK logic would otherwise indicate for
the SMLINK[0] pin.
1 = The SMLINK[0] pin is Not overdriven low. The other
SMLINK logic controls the state of the pin.
This read-only bit has a default value that is dependent
on an external signal level.
SMLINK1_CUR_ This pin returns the value on the SMLINK[1] pin. This
STS
allows software to read the current state of the pin.
0 = Low
1 = High
Bit Reset
Value
0h
1b
1b
Bit Access
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
916
August 2009
Order Number: 320066-003US