EP80579 Datasheet, PDF (602/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.3
Offset 40h: DCALCSR – DDR Calibration Control and Status Register
This CSR is in the memory-mapped IO region of Bus 0, Device 0, Function 0 of the
memory controller. The SMRBASE register described in Section 16.1.1.9, “Offset 14h:
SMRBASE - System Memory RCOMP Base Address Register” on page 395, provides the
base address for these registers. The offsets listed for the following registers are
relative to this base address.
The value for BAR for all registers in this section is BAR14h.
Note: DCALCSR is used only for calibration. MBCSR is used for Memory Test.
Table 16-223.Offset 40h: DCALCSR – DCAL Control and Status Register (Sheet 1 of 2)
Description: DCALCSR - DCAL Control and Status Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 40h
Offset End: 43h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30 :28
27
26
25 :24
23
22 :21
Bit Acronym
Bit Description
Sticky
START
Start Operation
When set to 1 by software, the operation selected by
the DCALCSR.OPCODE is initiated. Hardware clears this
N
bit when the operation is complete.
Completion Status
FAIL
1xx = Fail, 0xx = Pass
N
Note: Best practice is to rely on MemBIST following
calibration to confirm a reliable DRAM interface.
Basic Data Pattern Enable: This controls which data
pattern is used for the DQS Delay calibration. Setting
this field enables the use of the basic data pattern
BASPAT selected by the DCALCSR.PATTERN bits. When cleared, N
the extended data pattern specified in the DDQSCVDP
and DDQSCADP registers is used. Note: extended data
pattern mode is not to be used in 2T configurations.
Reset Registers in Single Step Mode: Reset
DCALDATA CSR in single step calibration mode. This bit
should be set during the first step of a single step
RSTREGSS calibration. It will enable hardware to clear all registers N
and status bits during the calibration step the same way
hardware does on the first step of an automatic “all
passes” calibration.
Reserved Reserved
N
Single Step Calibration Operation:
Applies only to Receive enable and DQS cal.
“1” = Single step - a single step of the algorithm
SGLSTP
selected by the DCALCSR.OPCODE is run by hardware.
N
No data analysis is run.
“0” = All passes - all steps of the algorithm selected by
the DACLCSR.OPCODE is run by hardware including
data analysis.
Chip select:
This field corresponds to the chip select outputs:
CS[1:0]. This field Applies to NOP, Refresh, Precharge
all, and MRS/EMRS commands. It also applies to
Receive Enable, and DQS Delay cal in single step mode.
01: select Rank 0
CS
10: select Rank 1
N
00: Reserved
11: Reserved
Note: Set CS to 01 for Self Refresh Entry. Hardware
will automatically detect presence of a second
rank/DIMM and sequence Self Refresh Entry via
both chip selects if necessary.
Bit Reset
Value
0b
000b
0b
0b
00b
0b
00b
Bit Access
RWS
RW
RW
RW
RO
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
602
August 2009
Order Number: 320066-003US