EP80579 Datasheet, PDF (1224/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.19 Offset 20h: MEMB – Memory Base Register
This register specifies the starting memory address of devices in the AIOC
infrastructure. The range is aligned to a 1M boundary, so address bits [19:0] are
assumed to be zero.
Table 34-21. Offset 20h: MEMB: Memory Base Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 20h
Offset End: 21h
Size: 16 bit
Default: FFF0
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 04
03 : 00
MEMB
RV
These bits correspond to address bits [31:20] of the
transaction.
Reserved
Sticky
Bit Reset
Value
Bit Access
FFFh
RW
0h
RO
34.2.2.20 Offset 22h: MEML – Memory Limit Register
This register specifies the ending memory address of devices in the AIOC
infrastructure. The range is aligned to a 1M boundary, so address bits [19:0] are
assumed to be FFFFF.
Table 34-22. Offset 22h: MEML: Memory Limit Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 22h
Offset End: 23h
Size: 16 bit
Default: 0
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 04
03 : 00
MEML
RV
These bits correspond to address bits [31:20] of the
transaction.
Reserved
Sticky
Bit Reset
Value
Bit Access
0h
RW
0h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1224
August 2009
Order Number: 320066-003US