EP80579 Datasheet, PDF (1319/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.12
35.12.1
Expansion Bus Configuration Space: Bus M, Device 8,
Function 0
The Expansion Bus is Device 8 of Bus M, and is accessed using type 1 configuration
cycles.
Register Details
Table 35-149.Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
09h
0Eh
10h
14h
2Ch
2Eh
34h
3Ch
3Dh
40h
DCh
DDh
DEh
E0h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
F1h
01h
03h
05h
07h
08h
0Bh
0Eh
13h
17h
2Dh
2Fh
34h
3Ch
3Dh
43h
DCh
DDh
DFh
E1h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
F1h
“Offset 00h: VID: Vendor Identification Register” on page 1320
8086h
“Offset 02h: DID: Device Identification Register” on page 1320
503Dh
“Offset 04h: PCICMD: Device Command Register” on page 1321
0000h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1321
0010h
“Offset 08h: RID: Revision ID Register” on page 1322
Variable
“Offset 09h: CC: Class Code Register” on page 1323
068000h
“Offset 0Eh: HDR: Header Type Register” on page 1323
00h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1323
00000000h
“Offset 14h: MMBAR: Expansion Bus Base Address Register” on page 1324
00000000h
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1325
0000h
“Offset 2Eh: SID: Subsystem ID Register” on page 1325
0000h
“Offset 34h: CP: Capabilities Pointer Register” on page 1326
DCh
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1326
00h
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1326
01h
“Offset 40h: LEBCTL: LEB Control Register” on page 1327
00h
“Offset DCh: PCID: Power Management Capability ID Register” on page 1327
01h
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1328
E4h
“Offset DEh: PMCAP: Power Management Capability Register” on page 1328
0023h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1329
0000h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1329
09h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1330 F0h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1330
09h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1330
01h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1331
00h
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1331
00h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1332
05h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
page 1332
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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